PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES

• US 20100329058A1
• Filed: 08/25/2010
• Published: 12/30/2010
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Hong-Yi Chen, Jason Sheu, Jason T. Su, Jensen Tjeng, Sehat Sutardja
• Inventors: Sutardja, Sehat, Chen, Hong-Yi, Sheu, Jason, Tjeng, Jensen, Su, Jason T.
• Granted Patent: US 8,089,823 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.

Claims

1. A processor comprising:

a cache memory that comprises;

an array of cells;

a plurality of word lines; and

a plurality of bit lines; and

a control module that enables a word line of said plurality of word lines to access a first cell in said word line, that disables said word line, and that maintains said word line in a disabled state to access a second cell in said word line.