STORAGE OF DIGITAL DATA

• US 20100332528A1
• Filed: 09/10/2010
• Published: 12/30/2010
• Est. Priority Date: 03/15/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Dellow, Andrew R.
• Granted Patent: US 8,391,483 B2
• Time in Patent Office: Days
• US Class Current: 707/769
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4334 Recording operations recording of a television signal H04N5/76; arrangements for recording or accumulating broadcast information or broadcast-related information H04H60/27
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4408 involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 21/462 Content or additional data management, e.g. creating a master electronic program guide from data received from the Internet and a Head-end, controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
• CPC Class Codes: H04N 5/76 Television signal recording
• CPC Class Codes: H04N 5/913 for scrambling ; for copy protection

Abstract

A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Claims

1. A digital apparatus, for a first value contained at a variable location that comprises only part of a second value having a predetermined number of input bits, a corresponding third value, the apparatus comprising:

(a) a table circuit to store a table containing the third value and, for each third value, the second value comprising the predetermined number of bits with the first value contained at the variable location in the second value and with zero values elsewhere;

(b) a fourth value storing circuit formed unitary with the table circuit to store a fourth value corresponding to respective third value, each comprising the same predetermined number of bits as the second value with ones contained at the variable location and zero values elsewhere;

(c) a combining circuit coupled to the fourth value storing circuit and structured to combine a received input second value and the fourth value and adapted to provide a combined value consisting of a value held in the input second value at the variable location and zeros elsewhere; and

(d) a comparing circuit coupled to the table circuit and the combining circuit to compare the combined value and the second value stored in the table and, (i) when they are not equal, utilizing a register circuit to repeat the operations of the combining circuit and the comparing circuit for a next second value and corresponding mask and DES key value stored in the table, and (ii) when they are equal, providing the corresponding third value as an output value.

2. The apparatus of claim 1, in which said table is divided into regions, each region corresponding to a respective format for said second value.

3. The apparatus of claim 1, comprising a read circuit coupled to the table circuit to read the third value from the table circuit.

4. The apparatus of claim 1, wherein the first value comprises a program identification, the second value comprises a packet header, the third value comprises a data encryption standard key value, and the fourth value comprises a mask value.

5. A digital method for locating, for a first value contained at a variable location that comprises only part of a second value having predetermined number of input bits, a corresponding third value, the method comprising the steps of:

(a) storing in a table containing the third value, a corresponding second value having the predetermined number of bits with the first value contained at a variable location in the second value and with zero values elsewhere;

(b) storing fourth values in the table that correspond to the third value, each fourth value having the same predetermined number of bits as the second value with ones contained at the variable location and zero values elsewhere;

(c) receiving an input second value having the predetermined number of bits;

(d) combining the input second value and one of the fourth values and providing a combined value consisting of a value held in the input second value at the variable location and zeros elsewhere; and

(e) comparing the combined value and the second value stored in the table and, (i) when they are not equal, incrementing in the table to a next second value and corresponding third and fourth values and repeating the operations of the combining and comparing for the incremented second value stored in the table, and (ii) when they are equal, reading the corresponding third value from the table and providing it as an output value.

6. The method of claim 5, in which the table is divided into regions, each region corresponding to a respective format for the second value.

7. The method of claim 5, wherein the first value comprises a program identification, the second value comprises a packet header, the third value comprises a data encryption standard key value, and the fourth value comprises a mask value.

8. A circuit, comprising:

a digital apparatus for locating, for a first value contained at a variable location that comprises part only of a second value predetermined number of input bits, a corresponding third value, the apparatus comprising;

(a) a table store for storing a table containing the third value and, for each third value, a second value corresponding to respective third values comprising the predetermined number of bits with a first value contained at a variable location in the second value and with zero values elsewhere;

(b) a fourth value store formed unitary with the table store for storing fourth values, each fourth value comprising the same number of bits as the predetermined number of bits as the second values with ones contained at the variable location and zero values elsewhere;

(c) an input for receiving an input second value comprising the same number of bits as the predetermined number of bits;

(d) a combiner coupled to the fourth value store and the input to combine the input second value and one of the fourth values and adapted to provide a combined value consisting of a value held in the input second value at the variable location and zeros elsewhere;

(e) a read circuit coupled to the table store to read the third value from the table store; and

(f) a comparator coupled to the table store and the combiner for comparing the combined value and one of the second values stored in the table store and, (i) when they are not equal, utilizing a register circuit to repeat the operations of the combiner and the comparator for the next second value and corresponding mask and third value stored in the table store, and (ii) when they are equal, enabling the read circuit to read the corresponding third value from the table in the table store and providing it as an output value.

9. The apparatus of claim 8, wherein the first value comprises a program identification, the second value comprises a packet header, the third value comprises a data encryption standard key value, and the fourth value comprises a mask value.

10. The circuit of claim 8, in which the table store is divided into regions and each region corresponds to a respective format for the second value.