PROCESSING UNIT

• US 20100332573A1
• Filed: 06/29/2010
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hondou, Mikio
• Granted Patent: US 8,533,248 B2
• Time in Patent Office: Days
• US Class Current: 708/231
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/548 Trigonometric functions; Co-ordinate transformations

Abstract

A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<<63) and a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? 1.0: rs1)̂(rs2 [1]<<63), or a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜rs2 [0]<<63) and a fourth trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1: 1.0)̂((rs2 [1]̂rs2 [0])<<63)).

Claims

1. A processing unit, comprising:

a floating point multiply-add circuit which receives three inputs, which are rs1, rs2 and rs3, and executes floating point multiply-add operation;

a resistor file of which the floating point multiply-add circuit use,

an OR circuit which computes OR of the most significant bit of output of the floating point multiply-add circuit and the least significant bit rs2 [0] of the input rs2;

a selector which selects either the input rs1 or the value “

1.0”

; and

an EOR circuit which computes EOR of a bit rs2 [1] that is one bit higher than the least significant bit of the input rs2 and the most significant bit of the selector,

wherein the floating point multiply-add circuit computes an expansion point, determines an expansion function of the Taylor series expansion of a trigonometric function and computes the expansion function according to computed the expansion point and determined the expansion function,

and said selector, said OR circuit and said EOR circuit output a coefficient of a polygonal of said determined expansion function according trigonometric function operation auxiliary instruction.

3. The processing unit according to claim 1, wherein the trigonometric function is a sine function,

and wherein said trigonometric function operation auxiliary instruction comprises:

a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|(rs2 [0]<

<

63); and

a second trigonometric function operation auxiliary instruction for defining the operation of rd=((rs2 [0])?1.0;

rs1)̂

(rs2 [1]<

<

63).

5. The processing unit according to claim 1, further comprising a second selector which selects the input rs1 or input rs2, and outputs the selected input to the floating point multiply-add computing unit according to said trigonometric function operation auxiliary instruction.

7. The processing unit according to claim 1, further comprising:

a coefficient table which stores a coefficient of each degree of the Taylor series of the trigonometric function; and

a circuit that reads a coefficient of the coefficient table using the computed expansion function,

wherein the floating point computing unit executes the Taylor series operation of the trigonometric function using the computed expansion point and the coefficient which has been read.

2. A processing unit, comprising:

a floating point multiply-add circuit which receives three inputs, which are rs1, rs2 and rs3, and executes floating point multiply-add operation;

an OR circuit which computes OR of the most significant bit of output of the floating point multiply-add circuit and an inversion signal of the least significant bit rs2 [0] of the input rs2;

a selector that selects either the input rs1 or the value “

1.0”

;

a first EOR circuit that computes EOR of a bit rs2 [1] that is one bit higher than the least significant bit of the input rs2; and

a second EOR circuit that computes EOR of the most significant bit of the selector and output of the first EOR circuit,

wherein the floating point multiply-add circuit computes an expansion point, determines an expansion function of the Taylor series expansion of a trigonometric function and computes the expansion function according to computed the expansion point and determined the expansion function,

and said selector, said OR circuit and said first and second EOR circuits output a coefficient of a polygonal of said determined expansion function according trigonometric function operation auxiliary instruction.

4. The processing unit according to claim 2, wherein the trigonometric function is a cosine function,

and wherein said trigonometric function operation auxiliary instruction comprises:

a third trigonometric function operation auxiliary instruction for defining the operation of rd=(rs1*rs1)|((˜

rs2 [0])<

<

63); and

a fourth trigonometric function auxiliary instruction for defining the operation of rd=((rs2 [0])? rs1;

1.0)̂

((rs2 [1]̂

rs2 [0])<

<

63)).

6. The processing unit according to claim 2, further comprising a second selector which selects the input rs1 or input rs2, and outputs the selected input to the floating point multiply-add computing unit according to said trigonometric function operation auxiliary instruction.

8. The processing unit according to claim 2, further comprising:

a coefficient table that stores a coefficient of each degree of the Taylor series of the trigonometric function; and

a circuit that reads a coefficient of the coefficient table using the computed expansion function,

wherein the floating point computing unit executes the Taylor series operation of the trigonometric function using the computed expansion point and the coefficient which has been read.