STRUCTURE AND METHOD FOR MANAGING WRITING OPERATION ON MLC FLASH MEMORY

• US 20100332726A1
• Filed: 06/26/2009
• Published: 12/30/2010
• Est. Priority Date: 06/26/2009
• Status: Abandoned Application

• Current Assignee: Solid State System Co., Ltd.
• Original Assignee: Solid State System Co., Ltd.
• Inventors: Wang, Chih-Hung
• Application Number:
  US12/492,158
• Publication Number:
  US 20100332726A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies

Abstract

A method for managing a writing operation for a multi-level cell (MLC) nonvolatile memory by a host is provided. The MLC nonvolatile memory has a plurality of MLC blocks, each MLC cell of each MLC block can store multiple logical data bits. The method includes forming a turbo writing unit from the spare block pool; writing a data sent by the host to the turbo writing unit; and changing the role of the turbo writing unit into a turbo data unit. The turbo writing unit is formed with at least one of the MLC blocks, each MLC cell of the at least one of the MLC blocks stores a portion of the logical data bits the MLC cell is capable of storing.

Claims

1. A method for managing a writing operation from a host for a multi-level cell (MLC) nonvolatile memory having multiple MLC blocks, the method comprising:

arranging a spare block pool comprising at least a portion of the MLC blocks of the MLC nonvolatile memory available to be allocated for writing data;

forming a turbo writing unit from a spare block pool;

writing a data sent by the host to the turbo writing unit;

after finishing writing the turbo writing unit, the turbo writing unit is treated as a turbo data unit; and

copying the data stored in the turbo data unit into one of the MLC blocks allocated from the spare-block pool to replace the turbo data unit,

wherein the turbo writing unit is formed with at least one of the MLC blocks, not all of the MLC cells of the at least one of the MLC blocks store data with all of the logical data bits on which the MLC cell is capable of storing.

2. The method of claim 1, wherein the step of forming the turbo writing unit is to form the turbo writing unit with two of the MLC blocks, wherein each of the MLC cell of the MLC blocks has a storage capacity of two logical data bits.

3. The method of claim 2, wherein each of the MLC cell stores at least one logical data bit while it is capable of storing two logical data bits.

4. The method of claim 1, wherein the step of forming the turbo writing unit is forming the turbo writing unit with three of the MLC blocks, wherein each of the MLC cell of the MLC blocks has a storage capacity of three logical data bits.

5. The method of claim 4, wherein each MLC cell stores at least one logical data bit while the MLC cell of the MLC blocks is capable of storing three logical data bits.

6. The method of claim 1, wherein the step of forming the turbo writing unit is performed when the total number of the turbo writing units and the turbo data unit in use doesn'"'"'t exceed a presetable threshold.

7. The method of claim 1, wherein the turbo writing unit is formed to write the data from the host when the total number of the available MLC blocks in the spare block pool is larger than a presetable threshold.

8. The method of claim 1, further comprising copying the data stored in the turbo data unit into one of the MLC blocks allocated from the spare block pool to serve as a data block for replacing the turbo data unit.

9. A block structure for a multi-level cell (MLC) nonvolatile memory, the MLC nonvolatile memory having a plurality of MLC blocks, each MLC cell of each MLC block can store multiple bits of data, the block structure comprising:

a spare block pool, comprising at least a portion of the MLC blocks of the MLC nonvolatile memory available to be allocated for writing data;

a turbo writing unit, allocated from the spare block pool for storing data from a host, wherein the turbo writing unit comprises at least one of the MLC blocks, not all of the MLC cells of the at least one of the MLC blocks store data with all of the logical data bits on which the MLC cell is capable of storing;

.

a turbo data unit, wherein after finishing writing data to the turbo writing unit, the turbo writing unit is treated as the turbo data unit; and

a data block, as one of the MLC blocks allocated from the spare block pool for storing the data copied from the turbo data unit.

10. The block structure of claim 9, wherein the turbo writing unit comprises two blocks of the MLC blocks.

11. The block structure of claim 10, wherein each MLC cell has a storage capacity of two logical data bits.

12. The block structure of claim 9, wherein the turbo writing unit comprises three blocks of the MLC blocks.

13. The block structure of claim 12, wherein each MLC cell has a storage capacity of three logical data bits.

14. The block structure of claim 9, wherein the turbo writing unit is allocated to write the data from the host when the total number of the sum of the turbo data units and the turbo writing units in use doesn'"'"'t exceed a preset threshold.

15. The block structure of claim 9, wherein the turbo writing unit-is allocated to write the data from the host when the total number of the available MLC blocks in the spare block pool is larger than a preset threshold.