METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY

• US 20100332730A1
• Filed: 06/30/2009
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Faber, Robert, Royer, Robert J. JR., Chartrand, Brent
• Granted Patent: US 8,612,666 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.

Claims

1. An apparatus comprising:

a NAND flash memory;

a logical-to-physical (LTP) address mapping structure associated with the NAND flash memory, the structure including one or more segments; and

a controller coupled with the NAND flash memory to facilitate paging of the one or more segments of the structure to the NAND flash memory.

2. The apparatus of claim 1, wherein a size of each segment of the LTP address mapping structure is the same as or a multiple of a page size of the NAND flash memory.

3. The apparatus of claim 1, wherein the controller to facilitate paging of the one or more segments of the structure is to:

receive a request to write the one or more segments to the NAND flash memory;

determine that an erase block of the NAND flash memory is available responsive to receiving the request; and

write at least one of the one or more segments to the determined erase block.

4. The apparatus of claim 1, wherein the controller is a block storage driver.

5. A system comprising:

a NAND flash memory to store a plurality of sections of an indirection system map of the NAND flash memory; and

logic to cache one or more of the plurality of sections of the indirection system map in a memory in the system.

6. The system of claim 5, wherein the logic is further to store a lookup table in the memory, the lookup table associated with the indirection system map to indicate a location of each section of the indirection system.

7. The system of claim 5, wherein the indirection system map comprises a logical-to-physical address mapping structure of the NAND flash memory.

8. The system of claim 6, wherein a size of each section of the indirection system map is equal to or a multiple of a page size of the NAND flash memory.

9. The system of claim 8, wherein the logic to store the lookup table is to:

store a pointer to each section of the indirection system map cached in the memory; and

store a physical page address of each section of the indirection system map not cached in the memory.

10. The system of claim 8, wherein the logic is further to determine that one section of the indirection system not cached in the memory comprises contiguous physical addresses for all entries in the one section, and wherein the logic to store the lookup table is to:

store a physical address corresponding to a first entry of a logical address of the determined section; and

indicate the determined one section as optimized.

11. The system of claim 8, wherein the logic is further to divide an unused portion of the memory into a plurality of buffers, and wherein the logic to cache the one or more sections of the indirection system map in the memory is to cache the one or more sections of the indirection system map into the plurality of buffers.

12. The system of claim 11, wherein the logic is further to:

determine that the lookup table is to indicate that a section of the indirection system to be accessed is not cached in the memory; and

determine if any of the plurality of buffers in the memory is unused, if so,

cache the section of the indirection system to be accessed from the NAND flash memory into the determined unused buffer in the memory; and

if not so,

select one or more sections of the indirection system cached in one or more respective buffers to be evicted to the NAND flash memory based on a caching policy;

evict the selected one or more sections of the indirection system to the NAND flash memory; and

cache the section of the indirection system to be accessed from the NAND flash memory into the one or more respective buffers of the memory.

13. The system of claim 5, wherein the logic is further to pin at least one of the cached one or more sections of the indirection system map in the memory, wherein the pinned segment is prevented from paging to the NAND flash memory.

14. The system of claim 5, wherein the memory is one of Synchronous Dynamic Random Access Memory, Dynamic Random Access Memory, RAMBUS DRAM and Double Data Rate three SDRAM.

15. A method comprising:

partitioning a logical-to-physical (LTP) indirection map of a non-volatile memory into a plurality of segments; and

paging at least one segment of the LTP indirection map to the non-volatile memory responsive to the partitioning.

16. The method of claim 15, wherein partitioning the LTP indirection map of the non-volatile memory into the plurality of segments comprises partitioning the LTP indirection map of the non-volatile memory into a plurality of page-sized segments.

17. The method of claim 15, further comprising maintaining a segment table associated with the LTP indirection map, wherein the segment table is to specify where each segment of the LTP indirection map is located.

18. The method of claim 15, wherein the non-volatile memory is a NAND flash memory, and wherein paging the at least one segment of the LTP indirection map to the NAND flash memory comprises:

determine that an erase block of the NAND flash memory does not contain any user data; and

write the at least one segment of the LTP indirection map to the determined erase block.

19. The method of claim 15 further comprising:

receiving a notification of power failure of the non-volatile memory;

determining that a size of the LTP indirection map is less than an unutilized memory space in a memory in response to receiving the notification;

building another LTP indirection map in the unutilized memory space in the memory; and

paging the other built LTP indirection map to the non-volatile memory.

20. The method of claim 17, wherein the non-volatile memory is a NAND flash memory, further comprising:

receiving a notification of power failure of the non-volatile memory;

determining that a size of the LTP indirection map is more than an unutilized memory space in a memory in response to receiving the notification;

identifying one or more erase blocks of the NAND flash memory storing the one or more segments of the LTP indirection map; and

building the segment table using the one or more stored segments of the LTP indirection map in the identified one or more erase blocks.