METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY
First Claim
Patent Images
1. An apparatus comprising:
- a NAND flash memory;
a logical-to-physical (LTP) address mapping structure associated with the NAND flash memory, the structure including one or more segments; and
a controller coupled with the NAND flash memory to facilitate paging of the one or more segments of the structure to the NAND flash memory.
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Abstract
A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.
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20 Claims
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1. An apparatus comprising:
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a NAND flash memory; a logical-to-physical (LTP) address mapping structure associated with the NAND flash memory, the structure including one or more segments; and a controller coupled with the NAND flash memory to facilitate paging of the one or more segments of the structure to the NAND flash memory. - View Dependent Claims (2, 3, 4)
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5. A system comprising:
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a NAND flash memory to store a plurality of sections of an indirection system map of the NAND flash memory; and logic to cache one or more of the plurality of sections of the indirection system map in a memory in the system. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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partitioning a logical-to-physical (LTP) indirection map of a non-volatile memory into a plurality of segments; and paging at least one segment of the LTP indirection map to the non-volatile memory responsive to the partitioning. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification