MEMORY SYSTEMS AND MAPPING METHODS THEREOF

• US 20100332732A1
• Filed: 01/27/2010
• Published: 12/30/2010
• Est. Priority Date: 06/29/2009
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chiang, Chun-Ying, Lu, Po-Ching
• Granted Patent: US 8,364,931 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s).

Claims

1. A memory system, comprising:

a flash memory; and

an interface device coupled between the flash memory and a host, storing a flash translation layer utilizing a block mapping table and a page mapping table to manage a plurality of data blocks and a plurality of log blocks of the flash memory by a page mapping scheme, and utilizing a random write page mapping table independent from the block mapping table and the page mapping table to manage a plurality of random write blocks of the flash memory by a random write mapping scheme.

2. The memory system of claim 1, wherein the block mapping table comprises a data block mapping table and a log block mapping table corresponding to the data block mapping table.

3. The memory system of claim 1, wherein the flash translation layer converts one of the data blocks corresponding to a logical block, into a random write block when following access to the logical block is a random single write operation.

4. The memory system of claim 3, wherein the flash translation layer determines whether the following access to the logical block is a random single write operation or a sequential data write operation according to access information provided from the host.

5. The memory system of claim 1, wherein the flash translation layer converts one of the random write blocks corresponding to a logical block into the data block when data stored into the converted random write block becomes cold data or following access to the logical block is a sequential data write operation.

6. The memory system of claim 1, wherein the flash translation layer converts one of the data blocks corresponding to a logical block and one of the log blocks corresponding to the converted data block into two random write blocks when data stored into the converted data block and the converted log blocks is hot data, or following access to the logical block is a random single write operation.

7. The memory system of claim 6, wherein the flash translation layer determines that data stored into the converted data block or the converted log block is hot data when the converted data block or the converted log block is full.

8. The memory system of claim 1, wherein when a number of the random write blocks converted corresponding to a logical block reaches a predetermined number, in which the predetermined number is larger than two, and the converted random write blocks are full, the flash translation layer performs a merge operation to the converted random write blocks.

9. A memory system, comprising:

a flash memory; and

an interface device coupled between the flash memory and a host, storing a flash translation layer, and utilizing a data block mapping table, a log block mapping table and a page mapping table to manage a first data block of the flash memory by a page mapping scheme, wherein the flash translation layer converts the first data block into a first random write block and utilizes a random write page mapping table independent from the block mapping table, the log block mapping table and the page mapping table to manage the first random write block when following access to a first logical block of the flash memory is a random single write operation.

10. The memory system of claim 9, wherein the flash memory further comprises a first log block corresponding to the first data block, and the flash translation layer converts the first data block and the first log block into the first random write block and a second random write block respectively and utilizes the random write page mapping table to manage the first and second random write blocks when the following access to the first logical block is a random single write operation.

11. The memory system of claim 10, wherein the flash translation layer determines whether the following access to the first logical block is a sequential data write operation according to access addresses provided from the host.

12. The memory system of claim 9, wherein the flash memory further comprises a second data block corresponding to a second logical block and a log block corresponding to the second data block, and the flash translation layer converts the second data block and the log block into the second random write block and a third random write block respectively, and utilizes the random write page mapping table to manage the second and third random write blocks, when data stored in the second data block and the log block is hot data.

13. The memory system of claim 12, wherein the flash translation layer assigns a fourth data block for the second logical block, copies valid data stored in the second and third random write blocks into the third data block and manages the third data block by the page mapping scheme, when the data stored in the second and third random write blocks becomes cold data.

14. The memory system of claim 12, wherein the flash translation layer determines that data stored in the second data block and the log block is hot data, when the second data block and the log block are full.

15. The memory system of claim 10, wherein the flash translation layer assigns a space block of the flash memory to serve as a third random write block for the first logical block, when a first access to the first logical block is requested and the first and second random write blocks are full.

16. The memory system of claim 15, wherein the flash translation layer performs a merge operation to the first, second and third random write blocks, when a second access to the first logical block is requested and the first, second and third random write blocks are full.

17. The memory system of claim 10, wherein the flash translation layer assigns a space block of the flash memory to serve as a third random write block, and copies valid data in the first and second random blocks into the third random write block and erases the first and second blocks, when access to the first logical block is requested, the first and second random write blocks are full and a number of space blocks in the flash memory is lower than a predetermined number.

18. The memory system of claim 9, wherein the flash memory and the interface device form a memory card.

19. A mapping method for a memory system comprising a flash memory and an interface device coupled between the flash memory and a host, wherein the interface device stores a flash translation layer, comprising:

managing data blocks and log blocks of the flash memory by utilizing a data block mapping table and a page mapping table corresponding to the block mapping table by a page mapping scheme; and

managing random write blocks of the flash memory by utilizing a random page mapping table independent from the block mapping table and the page mapping table by a random write mapping scheme.

20. The mapping method of claim 19, further comprising converting one of the data blocks corresponding to a logical block into a random write block when following access to the logical block is a random single write operation.

21. The mapping method of claim 20, wherein whether following access corresponding to the logical block is a random single write operation or a sequential data write operation is determined according to access information provided from the host.

22. The mapping method of claim 19, further comprising converting one of the random write blocks corresponding to a logical block into a data block when data stored into the converted random write block is cold data or the following access to the logical block is a sequential data write operation.

23. The mapping method of claim 19, further comprising converting one of the data blocks corresponding to a logical block and one of the log blocks corresponding to the converted data block into two random write blocks when data stored into the converted data block and the converted log block is hot data or access to the logical block is a random single write operation.

24. The mapping method of claim 23, wherein the flash translation layer determines that the data stored into the converted data block and the converted log block is hot data when the converted data block and the converted log block are full.

25. The memory system of claim 19, further comprising performing a merge operation to a set of the random write blocks when a number of the set of the random write blocks corresponding to a logical block reaches a predetermined number and the set of the random write blocks are full, wherein the predetermined number is larger than two.

26. A mapping method for a memory system comprising a flash memory and an interface device coupled between the flash memory and a host, wherein the interface device stores a flash translation layer, comprising:

managing a first data block of the flash memory by utilizing a data block mapping table, a log block mapping table and a page mapping table by a page mapping scheme, and

converting the first data block into a first random write block and managing the first random write block by utilizing a random write page mapping table independent from the block mapping table, the log block mapping table and the page mapping table, when following access to a first logical block of the flash memory is a random single write operation.

27. The mapping method of claim 26, wherein the flash memory further comprises a first log block corresponding to the first data block, and the mapping method further comprises converting the first data block and the first log block into the first random write block and a second random write block respectively and managing the first and second random write blocks using the random write page mapping table, when the following access to the first logical block is a random single write operation.

28. The mapping method of claim 27, wherein whether the following access to the first logical block is a random single write operation or a sequential data write operation is determined according to access information provided from the host.

29. The mapping method of claim 26, wherein the flash memory further comprises a second data block corresponding to a second logical block and a log block corresponding to the second data block, and the mapping method further comprises converting the second data block and the log block into second and third random write blocks respectively and managing the second and third random write blocks utilizing the random write page mapping table, when data stored in the second data block and the log block is hot data.

30. The mapping method of claim 29, further comprising assigning a fourth data block for the second logical block, copying valid data stored in the second and third random write blocks into the third data block, and managing the third data block by the page mapping scheme, when data stored in the second and third random write blocks becomes cold data.

31. The memory system of claim 29, wherein the flash translation layer determines that the data stored in the second data block and the log block is hot data, when the second data block and the log block are full.

32. The memory system of claim 27, further comprising assigning a space block of the flash memory to serve as a third random write block for the first logical block when a first access to the first logical block is requested and the first and second random write blocks are full.

33. The memory system of claim 32, further comprising performing a merge operation to the first, second and third random write blocks, when a second access to the first logical block is requested and the first, second and third random write blocks are full.

34. The memory system of claim 27, further comprising performing a merge operation to the first and second random write blocks, assigning a space block of the flash memory to serve as a third random write block and copying valid data in the first and second random blocks into the third random write block, when access to the first logical block is requested, the first and second random write blocks are full and a number of space blocks in the flash memory is lower than a predetermined number.