SEMICONDUCTOR DEVICE HAVING MULTI ACCESS LEVEL AND ACCESS CONTROL METHOD THEREOF

• US 20100332783A1
• Filed: 06/08/2010
• Published: 12/30/2010
• Est. Priority Date: 06/25/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Youm, Yun-Ho, Noh, Mijung, Lee, Heonsoo, Park, Jaechul
• Granted Patent: US 8,347,116 B2
• Time in Patent Office: Days
• US Class Current: 711/164
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

Claims

1. A method of controlling access to an inner circuit in an interface circuit of a semiconductor device which includes the interface circuit and the inner circuit, the method comprising:

providing an inputted password as an input of a hash operator;

performing a hash operation in the hash operator and outputting a first hash value;

controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and

setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

2. The method as set forth in claim 1, further comprising, if the first and second hash values do not coincide while the hash operator repeatedly performs the hash operation the predetermined number of n times, prohibiting access to the inner circuit.

3. The method as set forth in claim 1, wherein setting an access level sets the access level with respect to the inner circuit at a highest level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide and sets the access level with respect to the inner circuit at a level corresponding to k if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide.

4. The method as set forth in claim 3, wherein the inner circuit comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide.

5. The method as set forth in claim 4, wherein the access level with respect to the inner circuit comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level.

6. The method as set forth in claim 1, wherein the nonvolatile memory storing the second hash value is an E-fuse memory.

7. The method as set forth in claim 1, wherein the interface circuit comprises a joint test action group (JTAG) interface.

8. A semiconductor device comprising:

an inner circuit;

a hash operator performing a hash operation with respect to an input and outputting a first hash value; and

a secure controller providing passwords inputted from the outside as an input of the hash operator and setting an access level with respect to the inner circuit according to a repetition number of times of the hash operation when a first hash value outputted from the hash operator and the second hash value stored in the nonvolatile memory coincide,

wherein the secure controller controls the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first and second hash values coincide.

9. The semiconductor device of claim 8, wherein the secure controller provides the first hash value outputted from the hash operator as an input of the hash operator repeatedly a maximum number of n (n is a positive integer) times, sets an access level with respect to the inner circuit at a highest access level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide, and sets an access level with respect to the inner circuit at a level corresponding to k if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide.

10. The semiconductor device of claim 8, wherein the second hash value stored in the nonvolatile memory is a hash value obtained by performing a hash operation on a password set by a user having the highest access level repeatedly the number of n times.

11. A method of controlling access in an interface circuit of a semiconductor device which includes the interface circuit, the method comprising:

providing an inputted password as an input of a hash operator;

performing a hash operation in the hash operator and outputting a first hash value;

controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and

setting an access level according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

12. The method as set forth in claim 11, further comprising, if the first and second hash values do not coincide while the hash operator repeatedly performs the hash operation the predetermined number of n times, prohibiting access.

13. The method as set forth in claim 11, wherein setting an access level sets the access level at a highest level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide and sets the access level at a level corresponding to k if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide.

14. The method as set forth in claim 13, wherein the semiconductor device comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide.

15. The method as set forth in claim 14, wherein the access level comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level.

16. The method as set forth in claim 11, wherein the nonvolatile memory storing the second hash value is an E-fuse memory.

17. The method as set forth in claim 11, wherein the interface circuit comprises a joint test action group (JTAG) interface.