UNPACKING PACKED DATA IN MULTIPLE LANES

• US 20100332794A1
• Filed: 06/30/2009
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Orenstein, Doron, Hargil, Asaf
• Granted Patent: US 9,086,872 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand.

Claims

1. A method comprising:

receiving an instruction, the instruction indicating a first operand and a second operand, each of the first and second operands having a plurality of packed data elements that correspond in respective positions, a first subset of the packed data elements of the first operand and a first subset of the packed data elements of the second operand each corresponding to a first lane, and a second subset of the packed data elements of the first operand and a second subset of the packed data elements of the second operand each corresponding to a second lane; and

storing a result in response to the instruction, the result including;

(1) in the first lane, only lowest order data elements from the first subset of the first operand interleaved with corresponding lowest order data elements from the first subset of the second operand; and

(2) in the second lane, only highest order data elements from the second subset of the first operand interleaved with corresponding highest order data elements from the second subset of the second operand.

2. The method of claim 1, wherein the first lane comprises a lower lane and the second lane comprises an upper lane.

3. The method of claim 1, wherein the first lane comprises an upper lane and the second lane comprises a lower lane.

4. The method of claim 1, wherein the instruction includes a control field, wherein one or more bits of the control field correspond to the first lane and indicate that an unpack low operation is to be performed for the first lane, and wherein one or more bits of the control field correspond to the second lane and indicate that an unpack high operation is to be performed for the second lane.

5. The method of claim 1, wherein each of the first and second lanes has 128-bits.

6. The method of claim 1, wherein storing the result comprises:

in the first lane, storing only half of the data elements from the first subsets including storing the lowest order data elements from the first subset of the first operand in a same order as the lowest order data elements appear in the first subset of the first operand; and

in the second lane, storing only half of the data elements from the second subsets.

7. The method of claim 1, further comprising at least one of decoding the instruction into one or more instructions and translating the instruction into one or more instructions.

8. An apparatus comprising:

an execution unit that is operable as a result of an instruction to store a result,

in which the instruction has a first field to indicate a first operand and a second field to indicate a second operand, each of the first and second operands to have a plurality of packed data elements that are to correspond in respective positions, in which a first subset of the packed data elements of the first operand and a first subset of the packed data elements of the second operand are each to correspond to a first lane, and in which a second subset of the packed data elements of the first operand and a second subset of the packed data elements of the second operand are each to correspond to a second lane,

in which the result that is to be stored is to include;

(1) in the first lane, only lowest order data elements from the first subset of the first operand interleaved with corresponding lowest order data elements from the first subset of the second operand; and

(2) in the second lane, only highest order data elements from the second subset of the first operand interleaved with corresponding highest order data elements from the second subset of the second operand.

9. The apparatus of claim 8, wherein the first lane comprises a lower lane and the second lane comprises an upper lane.

10. The apparatus of claim 8, wherein the first lane comprises an upper lane and the second lane comprises a lower lane.

11. The apparatus of claim 8, wherein the instruction includes a control field, wherein one or more bits of the control field correspond to the first lane and indicate that the lowest order data elements of the first and second operands are to be unpacked, and wherein one or more bits of the control field correspond to the second lane and indicate that the highest order data elements of the first and second operands are to be unpacked.

12. The apparatus of claim 8, wherein the instruction has a third field, which is different than the first and second fields, to indicate a destination where the result is to be stored, and wherein storing the result comprises storing the result at the destination.

13. The apparatus of claim 8, wherein the instruction comprises a cross-lane unpack instruction.

14. The apparatus of claim 8, wherein each of the first and second lanes has 128-bits.

15. The apparatus of claim 8, wherein the execution unit is to store a result that comprises:

(1) in the first lane, only half of the data elements from the first subsets; and

(2) in the second lane, only half of the data elements from the second subsets.

16. The apparatus of claim 8, wherein the execution unit is to store a result that comprises, in the first lane, the lowest order data elements from the first subset of the first operand in a same order as the lowest order data elements appear in the first subset of the first operand.

17. The apparatus of claim 8, wherein the execution unit is to store a result that comprises at least four data elements each from one of the first and second operands.

18. The apparatus of claim 8, further comprising at least one of a decoder to decode the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result and an instruction translator to translate the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result.

19. The apparatus of claim 8, wherein the execution unit comprises a circuit, and

wherein the instruction comprises a machine instruction, and wherein the execution unit comprises particular logic operable to store the result due to the machine instruction.

20. An apparatus comprising:

a first 256-bit register to store a first source operand including a first data element represented by bits 0 through 31, a second data element represented by bits 32 through 63, a third data element represented by bits 64 through 95, a fourth data element represented by bits 96 through 127, a fifth data element represented by bits 128 through 159, a sixth data element represented by bits 160 through 191, a seventh data element represented by bits 192 through 223, and an eighth data element represented by bits 224 through 255;

a second 256-bit register to store a second source operand including a ninth data element represented by bits 0 through 31, a tenth data element represented by bits 32 through 63, an eleventh data element represented by bits 64 through 95, a twelfth data element represented by bits 96 through 127, a thirteenth data element represented by bits 128 through 159, a fourteenth data element represented by bits 160 through 191, a fifteenth data element represented by bits 192 through 223, and a sixteenth data element represented by bits 224 through 255;

an execution unit as a result of an instruction to store a result, the result that is to be stored to include the first data element to be stored to bits 0 through 31 of a destination register, the ninth data element to be stored to bits 32 through 63 of the destination register, the second data element to be stored to bits 64 through 95 of the destination register, the tenth data element to be stored to bits 96 through 127 of the destination register, the seventh data element to be stored to bits 128 through 159 of the destination register, the fifteenth data element to be stored to bits 160 through 191 of the destination register, the eighth data element to be stored to bits 192 through 223 of the destination register, and the sixteenth data element to be stored to bits 224 through 255 of the destination register.

21. The apparatus of claim 20, further comprising at least one of a decoder to decode the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result and an instruction translator to translate the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result.

22. An apparatus comprising:

a first 256-bit register to store a first source operand including a first data element represented by bits 0 through 31, a second data element represented by bits 32 through 63, a third data element represented by bits 64 through 95, a fourth data element represented by bits 96 through 127, a fifth data element represented by bits 128 through 159, a sixth data element represented by bits 160 through 191, a seventh data element represented by bits 192 through 223, and an eighth data element represented by bits 224 through 255;

a second 256-bit register to store a second source operand including a ninth data element represented by bits 0 through 31, a tenth data element represented by bits 32 through 63, an eleventh data element represented by bits 64 through 95, a twelfth data element represented by bits 96 through 127, a thirteenth data element represented by bits 128 through 159, a fourteenth data element represented by bits 160 through 191, a fifteenth data element represented by bits 192 through 223, and a sixteenth data element represented by bits 224 through 255;

an execution unit as a result of an instruction to store a result, the result that is to be stored to include the third data element to be stored to bits 0 through 31 of a destination register, the eleventh data element to be stored to bits 32 through 63 of the destination register, the fourth data element to be stored to bits 64 through 95 of the destination register, the twelfth data element to be stored to bits 96 through 127 of the destination register, the fifth data element to be stored to bits 128 through 159 of the destination register, the thirteenth data element to be stored to bits 160 through 191 of the destination register, the sixth data element to be stored to bits 192 through 223 of the destination register, and the fourteenth data element to be stored to bits 224 through 255 of the destination register.

23. The apparatus of claim 22, further comprising at least one of a decoder to decode the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result and an instruction translator to translate the instruction into one or more instructions that are to be executed by the execution unit to cause the execution unit to store the result.

24. A system comprising:

an interconnect;

a processor coupled with the interconnect, the processor including;

at least one of an instruction decoder, an instruction translator, and an instruction emulator, the at least one implemented in hardware, software, firmware, or a combination thereof, to receive an instruction, the instruction having a first field to indicate a first operand and a second field to indicate a second operand, each of the first and second operands to have a plurality of packed data elements that are to correspond in respective positions, in which a first subset of the packed data elements of the first operand and a first subset of the packed data elements of the second operand are each to correspond to a first lane, and in which a second subset of the packed data elements of the first operand and a second subset of the packed data elements of the second operand are each to correspond to a second lane; and

a circuit responsive to said at least one receiving the instruction to store a result, the result to include;

(1) in the first lane, only lowest order data elements from the first subset of the first operand interleaved with corresponding lowest order data elements from the first subset of the second operand; and

(2) in the second lane, only highest order data elements from the second subset of the first operand interleaved with corresponding highest order data elements from the second subset of the second operand; and

a dynamic random access memory (DRAM) coupled with the interconnect.

25. The system of claim 24, wherein the circuit is to store a result that comprises:

(1) in the first lane, only half of the data elements from the first subsets; and

(2) in the second lane, only half of the data elements from the second subsets.

26. An article of manufacture comprising:

a machine-readable medium to provide an instruction,

the instruction including a first field to indicate a first operand and a second field to indicate a second operand, each of the first and second operands to have a plurality of packed data elements that are to correspond in respective positions, a first subset of the packed data elements of the first operand and a first subset of the packed data elements of the second operand to each correspond to a first lane, and a second subset of the packed data elements of the first operand and a second subset of the packed data elements of the second operand to each correspond to a second lane, and

the instruction if processed by a machine to cause the machine to perform operations comprising storing a result, the result including;

(1) in the first lane, only lowest order data elements from the first subset of the first operand interleaved with corresponding lowest order data elements from the first subset of the second operand; and

(2) in the second lane, only highest order data elements from the second subset of the first operand interleaved with corresponding highest order data elements from the second subset of the second operand.

27. The method of claim 26, wherein the instruction comprises a machine instruction and the machine comprises particular logic operable to store the result due to the machine instruction.