PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION

• US 20100332865A1
• Filed: 07/12/2010
• Published: 12/30/2010
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: iGo, Inc.
• Original Assignee: iGo, Inc.
• Inventors: DuBose, Richard G.
• Granted Patent: US 7,908,498 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop

Abstract

A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10^th to 1/1000^th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.

Claims

1. A power supply having a primary side and a secondary side, said power supply comprising:

A primary circuit on the primary side;

a secondary circuit on the secondary side, wherein said secondary circuit is coupled to said primary circuit; and

a control circuit on the primary side, wherein said control circuit is configured to monitor at least one of a duty cycle or a switching rate within said primary circuit to detect an idle power mode, wherein said control circuit controls said primary circuit such that said primary circuit is substantially disabled in response to detection of said idle power mode.

2. The power supply of claim 1, wherein said control circuit comprises a logic control unit configured for monitoring said primary circuit and a power control unit configured for control of said primary circuit.

3. The power supply of claim 2, wherein said logic control unit and said power control unit comprise at least one of a combinational logic machine, a state machine or a microprocessor.

4. The power supply of claim 2, wherein said primary circuit comprises a modulator circuit configured for driving at least one of a transformer or a dielectric isolation device.

5. The power supply of claim 4, wherein said logic control unit is configured to monitor a signal of said modulator circuit.

6. The power supply of claim 4, wherein said power control unit is configured for control of at least one switch to control said modulator circuit.

7. The power supply of claim 4, wherein said modulator circuit comprises a PWM controller.

8. A primary side circuit configured to facilitate an ultra-low idle power mode in a power supply, said primary side circuit comprising:

a modulator configured for modulating input power at a high frequency rate to transfer power from a primary side of a transformer to a secondary side of the transformer; and

wherein said primary side circuit is in communication with a control circuit on a primary side of said power supply, and wherein said control circuit is configured to monitor at least one of a duty cycle or a switching rate of said modulator and to control said primary side circuit such that said primary side circuit is substantially disabled in response to said control circuit determining that substantially no load exists.

9. The primary side circuit of claim 8, wherein said control circuit comprises a logic control unit configured for monitoring said modulator and a power control unit configured for control of said primary side circuit.

10. The primary side circuit of claim 8, wherein said modulator comprises a PWM controller.

11. The primary side circuit of claim 9, wherein said logic control unit comprises at least one input coupled to said modulator to monitor said at least one of said duty cycle or said switching rate of said modulator.

12. The primary side circuit of claim 11, wherein said at least one input coupled to said modulator monitors at least one of an output pulse rate directly from a PWM controller within said modulator, an output from an integrator coupled to said PWM controller, and an output from a current-to-voltage converter coupled to said PWM controller.

13. The primary side circuit of claim 9, whereby said power control unit disables said modulator by opening at least one switch device coupled between said power control unit and said modulator.

14. A method for facilitating ultra-low power consumption in a power supply comprising:

monitoring, using a control circuit in communication with a primary circuit on a primary side of a power supply, at least one of a duty cycle or a switching rate of said primary circuit of said power supply and determining if a substantially no load condition exists; and

substantially disabling, using said control circuit, said primary circuit of said power supply in response to said substantially no load condition being detected.

15. The method according to claim 14, said method further comprising enabling said power supply in response to said control circuit determining a power load exists.

16. The method of claim 15, wherein said enabling said power supply occurs in response to at least one of a duty cycle or a switching rate of said primary circuit increasing above a threshold level.

17. The method of claim 14, wherein said monitoring comprises having a control circuit monitor the activity of a modulator to determine whether a substantially no load condition exists.

18. The method of claim 17, wherein said control circuit monitors at least one of an output pulse rate or a duty cycle directly from a PWM controller within said modulator.

19. The method of claim 17, wherein said control circuit monitors an output from a current-to-voltage converter coupled to a PWM controller within said modulator or an output from an integrator coupled to the PWM controller.

20. The method of claim 14, wherein said power supply is substantially disabled for an indeterminate period of time.