NON-VOLATILE MEMORY TO STORE MEMORY REMAP INFORMATION

• US 20100332895A1
• Filed: 06/30/2009
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Post, Samuel David, Leinwander, Mark, Bowers, Stephen, Billing, Gurkirat
• Granted Patent: US 8,412,987 B2
• Time in Patent Office: Days
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Subject matter disclosed herein relates to remapping memory devices.

Claims

1. A system comprising:

a controller to store digital signals representative of remap information regarding a memory device to a content-addressable memory (CAM), wherein said controller is adapted to store at least a portion of said remap information stored in said CAM into a nonvolatile, discretely-addressable memory if said remap information stored in said CAM is updated.

2. The system of claim 1, further comprising:

an error correction coding (ECC) decoder to receive digital signals representative of data read from said memory device and to determine a bit error rate and/or a number of bit errors associated with said read signals representative of said data, wherein said controller is adapted to store said remap information based at least in part on whether said bit error rate and/or said number of bit errors meets or exceeds an error threshold.

3. The system of claim 1, wherein said nonvolatile, discretely-addressable memory comprises a phase-change memory (PCM).

4. The system of claim 1, wherein said remap information comprises one or more tables of remap addresses.

5. The system of claim 1, wherein said nonvolatile, discretely-addressable memory is capable of being updated with new remap information on-the-fly, during a read/write process directed to said memory device.

6. The system of claim 1, wherein said CAM and said nonvolatile, discretely-addressable memory are substantially synchronous with one another.

7. The system of claim 1, wherein said nonvolatile, discretely-addressable memory comprises a second CAM.

8. A method comprising:

determining a bit error rate and/or a number of bit errors associated with digital signals representative of data read from a memory device; and

storing digital signals representative of remap information regarding said memory device in a nonvolatile, discretely-addressable memory, wherein said remap information is based at least in part on whether said bit error rate and/or said number of bit errors meets or exceeds an error threshold.

9. The method of claim 8, wherein said nonvolatile, discretely-addressable memory comprises a phase-change memory (PCM).

10. The method of claim 8, wherein said remap information comprises one or more tables of remap addresses.

11. The method of claim 8, wherein said nonvolatile, discretely-addressable memory is capable of being updated with new remap information on-the-fly, during a read/write process directed to said memory device.

12. The method of claim 8, wherein said nonvolatile, discretely-addressable memory comprises a content-addressable memory (CAM).

13. The method of claim 10, wherein said memory device comprises a main memory portion and a spare memory portion, and wherein said remap addresses correspond to a memory location in said spare memory portion.

14. The method of claim 8, wherein said storing further comprises writing said remap information into a portion of said nonvolatile, discretely-addressable memory, said portion being substantially the same size as said remap information.

15. A system comprising:

a host to read/write from/to a memory device and to execute one or more applications;

an error correction coding (ECC) decoder to receive digital signals representative of data read from said memory device and to determine a bit error rate and/or a number of bit errors associated with said read signals representative of said data; and

a remap controller to store digital signals representative of a remapped address of said memory device to a content-addressable memory (CAM) based at least in part on whether said bit error rate and/or said number of bit errors meets or exceeds an error threshold, wherein said CAM comprises a phase-change memory (PCM).

16. The system of claim 15, wherein said CAM is adapted to receive digital signals representative of a read address and to transmit digital signals representative of a signal responsive, at least in part, to whether said read address corresponds to said remapped address stored in said CAM.

17. The system of claim 16, further comprising:

a selection portion to select either said read address or said remapped address to be used as an address to read from said memory device, wherein said selection is based, at least in part, on said signal.

18. The system of claim 15, wherein said memory device comprises a main memory portion and a spare memory portion, and wherein said remapped address corresponds to a memory location in said spare memory portion.

19. The system of claim 18, wherein said memory device further comprises said ECC decoder and a phase-change memory portion.

20. The system of claim 15, wherein said bit en-or rate and/or said number of bit errors is responsive, at least in part, to a physical degradation of said memory.