Method and apparatus for scrubbing accumulated data errors from a memory system

• US 20100332900A1
• Filed: 06/24/2009
• Published: 12/30/2010
• Est. Priority Date: 06/24/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: MagiQ Technologies, Incorporated
• Inventors: Yang, Hsu Kai
• Granted Patent: US 9,170,879 B2
• Time in Patent Office: Days
• US Class Current: 714/16
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1096 Parity calculation or recalculation after configuration or reconfiguration of the system
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Claims

1. A data scrubbing apparatus for correcting disturb data errors occurring in an array of memory cells, the data scrubbing apparatus comprising;

an error flag detector for receiving an error flag signal indicating that an error has occurred during a read operation of a grouping of the memory cells within the array of memory cells; and

a write back control device for controlling writing back of data corrected subsequent to the read operation to the grouping of the memory cells.

2. The data scrubbing apparatus of claim 1 further comprising an address generator for selecting the grouping of the memory cells within the memory array and error correction code bits covering the grouping of memory cells.

3. The data scrubbing apparatus of claim 1 further comprising a data multiplexer for receiving provided data to be written to the array of the memory cells and the corrected data and upon receiving a write back signal from the write back control device, transferring the selected one of the provided data and the corrected data to the array of memory cells.

4. The data scrubbing apparatus of claim 1 wherein based on a scrub threshold value, the write back control device determines if the corrected data is to be written to the grouping of memory cells upon receipt of the error flag signal.

5. The data scrubbing apparatus of claim 4 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

6. The data scrubbing apparatus of claim 4 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal equal to a number of errors corrected in error correcting by error correcting circuitry within the array of memory cells.

7. The data scrubbing apparatus of claim 4 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of memory cells.

8. The data scrubbing apparatus of claim 1 wherein the write back control device suspends writing back during a writing of data to the array of memory cells.

9. The data scrubbing apparatus of claim 1 wherein the write back control device provides a busy indicator externally to the array of memory cells during a write back of corrected data.

10. The data scrubbing apparatus of claim 1 wherein the memory cells within the array of memory cells are SMT MRAM cells.

11. A memory device comprising:

a data scrubbing apparatus for correcting disturb data errors occurring in an array of memory cells within the memory device, the data scrubbing apparatus comprising;

an error flag detector for receiving an error flag signal indicating that an error has occurred during a read operation of a grouping of the memory cells within the array of memory cells; and

a write back control device for controlling writing back of data corrected subsequent to the read operation to the grouping of the memory cells.

12. The memory device of claim 11 wherein the data scrubbing apparatus further comprises an address generator for selecting the grouping of the memory cells within the memory array and error correction code bits covering the grouping of memory cells.

13. The memory device of claim 11 wherein the data scrubbing apparatus further comprises a data multiplexer for receiving provided data to be written to the array of the memory cells and the corrected data and upon receiving a write back signal from the address generator transferring the selected one of the provided data and the corrected data to the array of memory cells.

14. The memory device of claim 11 wherein based on a scrub threshold value, the write back control device determines if the corrected data is to be written to the grouping of memory cells upon receipt of the error flag signal.

15. The memory device of claim 14 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

16. The memory device of claim 14 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal equal to a number of errors corrected in error correcting by error correcting circuitry within the array of memory cells.

17. The memory device of claim 14 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of memory cells.

18. The memory device of claim 11 wherein the write back control device suspends writing back during a writing of data to the array of memory cells.

19. The memory device of claim 11 wherein the write back control device provides a busy indicator externally to the array of memory cells during a write back of corrected data.

20. The memory device of claim 11 wherein the memory cells within the array of memory cells are SMT MRAM cells.

21. A method for scrubbing disturb data errors occurring in an array of memory cells comprising:

determining that an error has occurred during a read operation of a grouping of the memory cells within the array of memory cells;

writing corrected data back to the grouping of memory cells if the number of errors in the grouping of memory cells exceeds a scrub threshold value;

22. The method for scrubbing disturb data errors of claim 21 wherein determining that an error has occurred comprises acquiring an error flag signal indicating that an error has occurred during a read operation of the grouping of the memory cells.

23. The method for scrubbing disturb data errors of claim 21 wherein writing corrected data back to the grouping of memory cells comprises generating an address for selecting the grouping of the memory cells within the memory array.

24. The method for scrubbing disturb data errors of claim 21 further comprising multiplexing provided data to be written to the array of the memory cells and the corrected data for transferring the selected one of the provided data and the corrected data to the array of memory cells.

25. The method for scrubbing disturb data errors of claim 22 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

26. The method for scrubbing disturb data errors of claim 22 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal equal to a number of errors corrected in error correcting by error correcting circuitry within the array of memory cells.

27. The method for scrubbing disturb data errors of claim 22 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of memory cells.

28. The method for scrubbing disturb data errors of claim 21 further comprises suspending writing back during a writing of provided data to the array of memory cells.

29. The method for scrubbing disturb data errors of claim 21 further comprising providing a busy indicator externally to the array of memory cells during a write back of corrected data.

30. The method for scrubbing disturb data errors of claim 21 wherein the memory cells within the array of memory cells are SMT MRAM cells.

31. An apparatus for scrubbing disturb data errors occurring in an array of memory cells comprising:

means for determining that an error has occurred during a read operation of a grouping of the memory cells within the array of memory cells;

means for writing corrected data back to the grouping of memory cells if the number of errors in the grouping of memory cells exceeds a scrub threshold value;

32. The apparatus for scrubbing disturb data errors of claim 31 wherein means for determining that an error has occurred comprises means for acquiring an error flag signal indicating that an error has occurred during a read operation of the grouping of the memory cells.

33. The apparatus for scrubbing disturb data errors of claim 31 wherein means for writing corrected data back to the grouping of memory cells comprises means for generating an address for selecting the grouping of the memory cells within the memory array.

34. The apparatus for scrubbing disturb data errors of claim 31 further comprising means for multiplexing provided data to be written to the array of the memory cells and the corrected data for transferring the selected one of the provided data and the corrected data to the array of memory cells.

35. The apparatus for scrubbing disturb data errors of claim 32 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

36. The apparatus for scrubbing disturb data errors of claim 32 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal equal to a number of errors corrected in error correcting by error correcting circuitry within the array of memory cells.

37. The apparatus for scrubbing disturb data errors of claim 32 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of memory cells.

38. The apparatus for scrubbing disturb data errors of claim 31 further comprises means for suspending writing back during a writing of provided data to the array of memory cells.

39. The apparatus for scrubbing disturb data errors of claim 31 further comprising means for providing a busy indicator externally to the array of memory cells during a write back of corrected data.

40. The apparatus for scrubbing disturb data errors of claim 31 wherein the memory cells within the array of memory cells are SMT MRAM cells.

41. An MRAM device comprising:

a data scrubbing apparatus for correcting disturb data errors occurring in an array of MRAM cells within the MRAM device, the data scrubbing apparatus comprising;

an error flag detector for receiving an error flag signal indicating that an error has occurred during a read operation of a grouping of the MRAM cells within the array of MRAM cells; and

a write back control device for controlling writing back of data corrected subsequent to the read operation to the grouping of the MRAM cells.

42. The MRAM device of claim 41 wherein the data scrubbing apparatus further comprises an address generator for selecting the grouping of the MRAM cells within the memory array and error correction code bits covering the grouping of MRAM cells.

43. The MRAM device of claim 41 wherein the data scrubbing apparatus further comprises a data multiplexer for receiving provided data to be written to the array of the MRAM cells and the corrected data and upon receiving a write back signal from the address generator transferring the selected one of the provided data and the corrected data to the array of MRAM cells.

44. The MRAM device of claim 41 wherein based on a scrub threshold value, the write back control device determines if the corrected data is to be written to the grouping of MRAM cells upon receipt of the error flag signal.

45. The MRAM device of claim 41 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each receipt of the error flag signal.

46. The MRAM device of claim 41 wherein the scrub threshold value indicates that the write back control device issues a write back signal after receipt of the error flag signal equal to a number of errors corrected in error correcting by error correcting circuitry within the array of MRAM cells.

47. The MRAM device of claim 41 wherein the scrub threshold value indicates that the write back control device issues a write back signal after each read cycle of the array of MRAM cells.

48. The MRAM device of claim 41 wherein the write back control device suspends writing back during a writing of data to the array of MRAM cells.

49. The MRAM device of claim 41 wherein the write back control device provides a busy indicator externally to the array of MRAM cells during a write back of corrected data.

50. The MRAM device of claim 41 wherein the MRAM cells within the array of MRAM cells are SMT MRAM cells.