METHOD FOR MANAGING DEVICE AND SOLID STATE DISK DRIVE UTILIZING THE SAME

• US 20100332922A1
• Filed: 03/11/2010
• Published: 12/30/2010
• Est. Priority Date: 06/30/2009
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chang, Ting-Chun, Chang, Po-Wei, Wang, Kuo-Hung, Hsieh, Kun-Hung, Tu, Li-Chun
• Application Number:
  US12/721,692
• Publication Number:
  US 20100332922A1
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.

Claims

1. A solid state disk drive, comprising:

a multiple level cell (MLC) memory device, comprising a plurality of memory blocks each comprising a plurality of memory cells capable of storing more than a single bit of data per cell; and

a controller, transforming at least one memory block into a single level cell (SLC)-like memory block, and accessing the memory block in an SLC manner.

2. The solid state disk drive as claimed in claim 1, wherein the controller further accesses the memory block, estimates a failure probability of the memory block according to the access operation, and transforms the memory block into an SLC-like memory block when the failure probability thereof exceeds a predetermined threshold.

3. The solid state disk drive as claimed in claim 2, wherein the processor estimates the failure probability of the memory block according to an amount of erase operations performed, a read failure rate, a write failure rate and/or a bit error rate of the memory block.

4. The solid state disk drive as claimed in claim 3, wherein the processor further obtains an erase count representing an amount of erase operations performed of the memory block, determines whether the erase count of the memory block has reached a predetermined erase count threshold, and transforms the memory block into the SLC-like memory block when the erase count of the memory block has reached

5. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether the access operation of the memory block has failed, and transforms the memory block into the SLC-like memory block when the access operation of the memory block has failed.

6. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether a bit error rate (BER) of the memory block corresponding to the access operation exceeds a predetermined BER threshold, and transforms the memory block into the SLC-like memory block when the BER of the memory block exceeds the predetermined BER threshold.

7. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner so that each memory cell of the memory block stores a single bit.

8. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant bits of the memory cells of the memory block.

9. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.

10. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.

11. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant pages of the memory cells of the memory block.

12. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with a first number of pages, each page is grouped into one of a second number of page groups in accordance with different page properties, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing a than the second number, and wherein the second number is a positive integer not less than the third number.

13. The solid state disk drive as claimed in claim 1, wherein the controller further transforms a predetermined number of memory blocks into SLC-like memory blocks, and wherein the predetermined number is dynamically adjusted by the controller in accordance with a predetermined rule.

14. A method for managing a memory device comprising a plurality of memory blocks each with a plurality of memory cells capable of storing more than a single bit of data per cell comprising:

receiving desired data in accordance with a write operation of the memory device;

estimating a failure probability of at least one memory block to be written corresponding to the write operation; and

writing the desired data to the memory cells of the memory block in a single level cell (SLC) manner when the estimated failure probability thereof exceeds a predetermined threshold.

15. The method as claimed in claim 14, further comprising:

transforming a predetermined number of memory blocks into SLC-like memory blocks; and

accessing the predetermined number of memory blocks in the SLC manner,

wherein the predetermined number is adjusted in accordance with a predetermined rule.

16. The method as claimed in claim 14, wherein each of the written memory cells stores a single bit.

17. The method as claimed in claim 14, wherein the desired data is only written to least significant bits of the memory cells.

18. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, and the desired data is only written to the first pages of the memory cells.

19. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and the desired data is only written to the first pages of the memory cells.

20. The method as claimed in claim 14, wherein the desired data is only written to least significant pages of the memory cells.

21. The method as claimed in claim 14, wherein the failure probability is estimated according to an amount of erase operations performed, a read failure rate, a

22. The method as claimed in claim 14, further comprising:

determining whether an erase count of the memory block has reached a predetermined erase count threshold; and

writing the desired data to the memory cells of the memory block in the SLC manner when the erase count of the memory block has reached the predetermined erase count threshold.

23. The method as claimed in claim 14, further comprising:

determining whether a previous write operation or a previous read operation of the memory block has failed; and

writing the desired data to the memory cells of the memory block in the SLC manner when the previous write operation or the previous read operation has failed.

24. The method as claimed in claim 14, further comprising:

determining whether a bit error rate (BER) of the memory block has exceeded a predetermined BER threshold; and

writing the desired data to the memory cells of the memory block in the SLC manner when the BER exceeds the predetermined BER threshold.

25. A solid state disk drive, comprising:

a multi-channel multiple level cell (MLC) memory device, comprising a plurality of memory modules each comprising a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, and each page is grouped into one of a plurality of page groups in accordance with different page properties; and

a controller, receiving at least one program command from a host to write desired data to the multi-channel MLC memory device, allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command, and writing the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.

26. The solid state disk drive as claimed in claim 25, wherein the page property is a program speed.

27. The solid state disk drive as claimed in claim 25, wherein the page property is an error correcting and checking (ECC) capability.

28. A method for managing a multi-channel memory device comprising a plurality of memory modules each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, comprising:

grouping each page into one of a plurality of page groups in accordance with different page properties;

receiving at least one program command to write desired data to the multi-channel MLC memory device;

allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command; and

writing the desired data in the empty pages,

wherein the empty pages allocated by the controller for an access operation belongs to the same page group.