SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY

• US 20100332923A1
• Filed: 06/29/2009
• Published: 12/30/2010
• Est. Priority Date: 06/29/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: D'ABREU, MANUEL ANTONIO, SKALA, STEPHEN, LEE, DANA
• Granted Patent: US 8,321,727 B2
• Time in Patent Office: Days
• US Class Current: 714/708
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.

Claims

1. A method comprising:

determining a rate of change of a performance parameter of a memory;

comparing the rate of change to a threshold; and

performing an action in response to determining that the rate of change satisfies the threshold.

2. The method of claim 1, wherein the performance parameter is an error count or an error frequency.

3. The method of claim 2, wherein an error-correcting code (ECC) engine provides the error count.

4. The method of claim 3, further comprising storing the error count in a log file.

5. The method of claim 4, further comprising retrieving the error count from the log file.

6. The method of claim 4, wherein the memory comprises a non-volatile memory and further comprising storing four ECC counts in the log file at the non-volatile memory.

7. The method of claim 6, wherein the rate of change is determined by evaluating each of the four stored ECC counts.

8. The method of claim 6, wherein the rate of change is determined based on a slope of a regression line determined based on each of the four stored ECC counts.

9. The method of claim 6, wherein the rate of change is a largest slope of a line between two ECC counts in the log file that correspond to a single region of the non-volatile memory.

10. The method of claim 1, wherein the performance parameter is a programming voltage.

11. The method of claim 1, wherein the performance parameter is an erase voltage.

12. The method of claim 1, wherein the memory is a flash memory, and wherein determining the rate of change, comparing the rate of change to the threshold, and performing the action occur at a controller of the flash memory.

13. The method of claim 1, wherein the threshold is a high water mark.

14. The method of claim 13, wherein the high water mark is adjustable.

15. The method of claim 13, wherein the high water mark is based on an average error count of a plurality of regions of a memory array in the memory.

16. The method of claim 13, wherein when the rate of change exceeds the high water mark, a region of the memory is marked as retired.

17. The method of claim 16, wherein the region is a block of the memory.

18. The method of claim 16, wherein the region is a page of the memory.

19. The method of claim 16, wherein the region is re-usable a predetermined number of times and when the predetermined number of times is reached, the region is marked as retired.

20. The method of claim 13, wherein when the rate of change exceeds the high water mark, a region of the memory is marked as probationary.

21. The method of claim 20, wherein the region is a block of the memory.

22. The method of claim 20, wherein the region is a page of the memory.

23. The method of claim 20, wherein a region marked as probationary is temporarily unavailable for use.

24. The method of claim 1, further comprising deactivating a region of the memory prior to the rate of change reaching a rate of change limit

25. A method comprising:

comparing a rate of change of a performance parameter of a memory to an adjustable threshold; and

modifying the adjustable threshold in response to a number of comparisons of the rate of change of the performance parameter satisfying the adjustable threshold.

26. The method of claim 25, wherein the threshold is adjusted each time a region of the memory is retired.

27. The method of claim 25, wherein the threshold is adjusted multiple times.

28. A method comprising:

comparing a rate of change of a performance parameter of a region of a memory to a threshold; and

selectively identifying the region as a non-used region based on a result of the comparison.

29. The method of claim 28, wherein the non-used region is retired or is placed on probation.

30. The method of claim 28, further comprising comparing a rate of change of a performance parameter of a plurality of regions of the memory to the threshold, wherein at least some of the plurality of regions are identified as non-used and others of the plurality of regions are identified as used based on the rate of change of the performance parameters for each of the plurality of regions.

31. A data storage device comprising:

a controller; and

a memory array including a plurality of regions;

wherein the controller is configured to selectively identify at least one region of the plurality of regions as a non-used region based on a rate of change of a performance parameter of the at least one region.

32. The data storage device of claim 31, wherein the non-used region is inaccessible.

33. The data storage device of claim 31, wherein the non-used region is permanently inaccessible.

34. The data storage device of claim 31, wherein the non-used region is temporarily inaccessible.

35. The data storage device of claim 31, wherein the at least one region of the plurality of regions is a block of the memory.

36. The method of claim 31, wherein the at least one region of the plurality of regions is a page of the memory.