THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE

• US 20110001172A1
• Filed: 09/14/2010
• Published: 01/06/2011
• Est. Priority Date: 03/29/2005
• Status: Abandoned Application

• Current Assignee: Sang-Yun Lee
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Application Number:
  US12/881,628
• Publication Number:
  US 20110001172A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/0101 Neon [Ne]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.

Claims

1. An apparatus, comprising:

an interconnect region; and

a multilayer semiconductor structure bonded to the interconnect region with a bonding region, the structure including two semiconductor regions having different electrical properties.

2. The apparatus of claim 1, wherein the structure includes a cleaved surface.

3. The apparatus of claim 1, wherein the structure includes a planarized surface.

4. The apparatus of claim 1, wherein the structure includes a planarized surface facing the bonding region.

5. The apparatus of claim 1, wherein the bonding region includes a metal layer bonded to a semiconductor layer.

6. The apparatus of claim 1, wherein the structure includes single crystalline semiconductor material.

7. The apparatus of claim 1, wherein the two semiconductor regions have opposite conductivity types.

8. The apparatus of claim 1, wherein the two semiconductor regions have the same conductivity type.

9. The apparatus of claim 1, wherein the structure includes a sidewall which extends between a surface and an opposed surface of the structure.

10. The apparatus of claim 1, wherein the structure includes an etched sidewall which extends between a surface and an opposed surface of the structure.

11. An apparatus, comprising:

an interconnect region having a conductive line;

a bonding region connected to the conductive line; and

a semiconductor structure coupled to the interconnect region with the bonding region, the structure including a planarized surface which faces the bonding region.

12. The apparatus of claim 11, wherein the bonding region includes a metal layer.

13. The apparatus of claim 11, wherein the structure includes two semiconductor regions having different electrical properties.

14. The apparatus of claim 11, wherein the structure includes a pn junction.

15. The apparatus of claim 11, wherein the bonding region establishes a bonding interface with the structure.

16. The apparatus of claim 11, further including a control dielectric adjacent to a sidewall of the structure.

17. The apparatus of claim 11, further including a control terminal, wherein the conductivity of the material of the structure is adjustable in response to adjusting a signal provided to the control terminal.

18. The apparatus of claim 11, further including a control terminal, wherein a current flow through the bonding region is adjustable in response to adjusting a signal provided to the control terminal.

19. The method of claim 11, wherein the bonding region covers a major surface of the interconnect region.

20. An apparatus, comprising:

an interconnect region; and

a multilayer semiconductor structure which includes first and second semiconductor layers having different electrical properties; and

a bonding region which couples the structure to the interconnect region through a bonding interface, wherein the structure includes a first planarized surface positioned proximate to the bonding region.

21. The apparatus of claim 20, wherein the structure consists essentially of blanket layers of semiconductor material.

22. The apparatus of claim 21, wherein the structure consists essentially of single crystal semiconductor material.

23. The apparatus of claim 22, further including a pn junction proximate to an interface between the first and second semiconductor layers.

24. The apparatus of claim 23, wherein the structure includes a second planarized surface, the pn junction being between the first and second planarized surfaces.