MEMS DEVICE AND INTERPOSER AND METHOD FOR INTEGRATING MEMS DEVICE AND INTERPOSER

• US 20110001198A1
• Filed: 02/01/2010
• Published: 01/06/2011
• Est. Priority Date: 01/02/2001
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Sawyer, William D.
• Granted Patent: US 8,809,135 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2203/0307 Anchors
• CPC Class Codes: B81B 7/0048 between the MEMS die and the substrate

Abstract

A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.

Claims

1. A method for manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to at least partially define said MEMS device;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOI wafer faces said interposer wafer;

removing said handle layer of said SOI wafer; and

removing said dielectric layer of the SOI wafer.

2. A method according to claim 1 further comprising:

etching said device layer of said SOI wafer to further define said MEMS device.

3. A method according to claim 2, wherein said etching said device layer of said SOI wafer to further define said MEMS device is performed by inductively coupled plasma (ICP) etch.

4. A method according to claim 2, wherein said etching said device layer of said SOI wafer to further define said MEMS device defines a proof mass.

5. A method of claim 1 further comprising etching said interposer wafer to further define a structure of said interposer wafer.

6. A method of claim 1, wherein the dielectric layer of the SOI wafer comprises silicon dioxide.

7. A method according to claim 1, wherein said bonding said SOI wafer to said interposer wafer comprises direct bonding.

8. A method according to claim 7, wherein said direct bonding of said SOI wafer to said interposer wafer comprises:

cleaning a top surface of said device layer of said SOI wafer and a top surface of said interposer wafer;

contacting said two top surfaces; and

annealing said two contacted wafers.

9. A method according to claim 1, wherein said bonding said SOI wafer to said interposer wafer comprises anodic bonding.

10. A method according to claim 1, wherein said bonding said SOI wafer to said interposer wafer comprises intermediate-layer bonding, wherein said intermediate layer material is adapted for wafer-to-wafer bonding.

11. A method according to claim 1, wherein said device layer is doped with a dopant concentration adapted to form said MEMS device.

12. A method according to claim 1, wherein said etching said device layer of said SOI wafer to at least partially define said MEMS device comprises etching said device layer to define posts of said MEMS device.

13. A method according to claim 1, wherein said etching said device layer of said SOI wafer to at least partially define said MEMS device comprises a mesa etch.

14. A method according to claim 1, wherein said interposer wafer is manufactured from an SOI wafer, wherein said interposer wafer comprises:

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer.

15. A method of claim 14, wherein the dielectric layer of the interposer wafer comprises silicon dioxide.

16. A method according to claim 14, wherein said obtaining an interposer wafer comprises forming said interposer wafer from said SOI wafer, wherein said forming said interposer wafer from said SOI wafer comprises:

(a) forming contacts on said device layer and said handle layer of said interposer wafer; and

(b) etching said device layer and said dielectric layer of said interposer wafer to define active areas on said interposer wafer.

17. A method according to claim 16 further comprising forming interconnect lines on said interposer wafer.

18. A method according to claim 16 further comprising a step of forming an oxide layer at a bottom surface of said handle layer of said interposer wafer before the step of forming contacts on said device layer and said handle layer of said interposer wafer.

19. A method of claim 16 further comprising depositing at least one heater on said handle layer of said interposer wafer.

20. A method of claim 16 further comprising depositing at least one sensor on said handle layer of said interposer wafer.

21. A Microelectromechanical Systems (MEMS) apparatus produced by a method according to claim 1.

41. A method according to claim 1, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

22. A method for manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to partially define said MEMS device;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOI wafer faces said interposer wafer;

removing said handle layer of said SOI wafer;

removing said dielectric layer of the SOI wafer; and

etching said device layer of said SOI wafer to further define said MEMS device.

23. A method according to claim 22, wherein said interposer wafer is manufactured from an SOI wafer, wherein said interposer wafer comprises:

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer.

42. A method according to claim 22, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

24. A method of manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining a first SOI wafer, wherein said first SOI wafer comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer and said dielectric layer to define separate areas on said first SOI wafer;

obtaining a second SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said second SOI wafer to at least partially define said MEMS device;

bonding said device layer of said second SOI wafer to said device layer of said first SOI wafer;

removing said handle layer of said second SOI wafer; and

removing said dielectric layer of said second SOI wafer.

25. A method according to claim 24 further comprising:

etching said device layer of said second SOI wafer to further define said MEMS device.

26. A Microelectromechanical Systems (MEMS) apparatus produced by a method according to claim 24.

43. A method according to claim 24, wherein said device layer of said second SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

27. A Microelectromechanical Systems (MEMS) apparatus comprising:

an interposer wafer comprising an SOI wafer, wherein said SOI wafer comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

a MEMS device comprising posts extending from a silicon plate, wherein said MEMS device is directly mounted to said interposer by bonding said posts of said MEMS device to said device layer of said interposer.

28. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device is mounted to said interposer without using brazing materials.

29. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device comprises a proof mass.

30. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device is produced by the following process:

obtaining a second SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said second SOI wafer to at least partially define said MEMS device;

bonding said device layer of said second SOI wafer to said device layer of said interposer wafer;

removing said handle layer of said second SOI wafer; and

removing said dielectric layer of said second SOI wafer.

31. A Microelectromechanical Systems (MEMS) apparatus according to claim 30, wherein said process further comprises etching said device layer of said second SOI wafer to further define said MEMS device.

32. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device is mounted to said interposer wafer by direct bonding.

33. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device is mounted to said interposer wafer by anodic bonding.

34. A Microelectromechanical Systems (MEMS) apparatus according to claim 27, wherein said MEMS device is mounted to said interposer wafer by intermediate-layer bonding, wherein said intermediate layer material is adapted for wafer-to-wafer bonding.

35. A method for etching an element in a structure, said structure including (i) a substrate, (ii) at least one device disposed on said substrate, and (iii) said element attached to said substrate and disposed over said device, said method comprising:

depositing and patterning resist on said element, such that at least one selected area of said element is covered by said resist, wherein said at least one selected area is above said at least one device; and

etching said element, whereby said at least one selected area covered by said resist is protected by said resist from being etched, whereby said at least one device under said area is protected from being etched.

36. A method of manufacturing a Microelectromechanical Systems (MEMS) assembly, said method comprising:

obtaining a first SOI wafer, wherein said first SOI wafer comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

performing a mesa etch on said device layer to define at least one structural post;

obtaining a second SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

bonding said device layer of said second SOI wafer to said at least one structural post of said first SOI wafer;

removing said handle layer of said second SOI wafer; and

removing said dielectric layer of said second SOI wafer.

37. A method according to claim 36 further comprising:

etching said device layer of said second SOI wafer to define said MEMS device.

38. A method according to claim 36 further comprising:

further etching said first SOI wafer to define a structure of an interposer.

44. A method according to claim 36, wherein said device layer of said second SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

39. A method for manufacturing Microelectromechanical Systems (MEMS) devices, said method comprising:

obtaining an SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

etching said device layer of said SOI wafer to define an array of sets of structural posts, wherein each set of structural post includes at least one structure post;

obtaining an interposer wafer;

bonding said SOI wafer to said interposer wafer in a way such that said device layer of said SOI wafer faces said interposer wafer;

removing said handle layer of said SOI wafer;

removing said dielectric layer of the SOI wafer;

etching said device layer of said SOI wafer to define an array of said MEMS devices; and

separating the result structure into individual MEMS devices.

45. A method according to claim 39, wherein said device layer of said SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.

40. A method of manufacturing Microelectromechanical Systems (MEMS) devices, said method comprising:

obtaining a first SOI wafer, wherein said first SOI wafer comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

performing a mesa etch on said device layer to define an array of sets of structural posts, wherein each set of structural post includes at least one structural post;

obtaining a second SOI wafer, which comprises;

(i) a handle layer,

(ii) a dielectric layer on said handle layer, and

(iii) a device layer on said dielectric layer;

bonding said device layer of said second SOI wafer to said at least one structural post of said first SOI wafer;

removing said handle layer of said second SOI wafer;

removing said dielectric layer of said second SOI wafer;

etching said device layer of said second SOI wafer to define an array of said MEMS devices; and

separating the result structure into individual MEMS devices.

46. A method according to claim 40, wherein said device layer of said second SOI wafer is characterized by a thickness and a conductivity adapted for forming the MEMS devices.