FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS

• US 20110001202A1
• Filed: 09/15/2010
• Published: 01/06/2011
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Donald S. Gardner, Fabrice Paillet, Gerhard Schrom, Peter Hazucha, Tanay Karnik
• Inventors: Paillet, Fabrice, Gardner, Donald S., Schrom, Gerhard, Hazucha, Peter, Karnik, Tanay
• Granted Patent: US 8,513,750 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Claims

1. A structure comprising:

a first layer of magnetic material and at least one via structure disposed in a first dielectric layer;

a second dielectric layer disposed on the first magnetic layer;

at least one conductive structure disposed in the second dielectric layer;

a third layer of dielectric material disposed on the conductive structure;

a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

2. The structure of claim 1 wherein the magnetic material comprises CoZrTa, CoNbTa, NiFe, CoP, CoPB, CoPRe, CoZr, CoZr Mo, FeCoAlN, CoZrTaN, FeCoP, CoPW, CoPBW, FeTaN, FeCoBSi, FeCoZrO, FeCoHfO, FeCoTiO, CoTi, FeCoB, CoZrOx, NiCuZnFeOx and combinations thereof.

3. The structure of claim 1 further comprising a conductive bump coupled to the at least one via, wherein the conductive bump is disposed on a passivation layer disposed on the second layer of magnetic material.

4. The structure of claim 1 wherein the dielectric layer comprises an ILD, wherein the ILD comprises a thickness of less than about 3.5 microns.

5. The structure of claim 1 wherein a distance between a top surface of the conductive structure and a bottom surface of the second layer of magnetic material comprises below about 0.5 micron.

6. The structure of claim 1 wherein a seed layer is disposed beneath the first and second layers of magnetic material.

7. The structure of claim 1 wherein the structure comprises a portion of a package substrate comprising a multilevel metallization CMOS structure.

8. The structure of claim 1 wherein the structure comprises a portion of at least one of an on-chip and an on-package voltage converter, an RF high-frequency circuit, an EMI noise reduction circuit and radar circuitry.