SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND SEMICONDUCTOR DEVICE MOUNTING METHOD

• US 20110001233A1
• Filed: 10/16/2007
• Published: 01/06/2011
• Est. Priority Date: 10/19/2006
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Nobori, Kazuhiro, Iwase, Teppei, Tomura, Yoshihiro
• Granted Patent: US 8,106,521 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83051 Forming additional members, e.g. dam structures
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding use resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding use resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling steps in mounting process of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.

Claims

1. A semiconductor device mounted structure comprising:

a semiconductor device having a plurality of device electrodes;

a board having a plurality of board electrodes;

a plurality of bump electrodes for connecting the device electrodes and the board electrodes to each other, respectively; and

a sealing-bonding use resin which seals the device electrodes, the board electrodes and the bump electrodes, respectively, and which is placed between the semiconductor device and the board so as to make the semiconductor device and the board bonded to each other, wherein

in the sealing-bonding use resin, a void portion is formed at a position corresponding to an edge portion or its proximity of the semiconductor device.

2. The semiconductor device mounted structure as defined in claim 1, wherein the void portion is a stress-relaxing void portion for relaxing stress generated in the resin by added external energy.

3. The semiconductor device mounted structure as defined in claim 1, wherein the void portion is formed at a position corresponding to a corner portion or its proximity of the generally rectangular-shaped semiconductor device.

4. The semiconductor device mounted structure as defined in claim 3, wherein a plurality of the void portions are placed in the resin just under all of the corner portions of the generally rectangular-shaped semiconductor device.

5. The semiconductor device mounted structure as defined in claim 3, wherein a recess portion is formed at a position on the board facing the corner portion of the semiconductor device, and an inner space of the recess portion is covered with the resin, whereby the void portion is formed.

6. The semiconductor device mounted structure as defined in claim 5, wherein the recess portion is formed on an upper surface of a recess-portion-forming board electrode which is formed on the board at a position facing the corner portion of the semiconductor device and which is not connected to any of the device electrodes.

7. The semiconductor device mounted structure as defined in claim 1, wherein the void portion is formed at a position corresponding to a side edge-line portion or its proximity of the generally rectangular-shaped semiconductor device.

8. The semiconductor device mounted structure as defined in claim 7, wherein the void portion is formed at every one of positions corresponding to all of four side edge-line portions or their proximities, excluding four corner portions and their proximities, of the generally rectangular-shaped semiconductor device.

9. The semiconductor device mounted structure as defined in claim 1, wherein the void portion is formed as an annular void portion at a position corresponding to the entire edge portion or its proximity of the semiconductor device.

10. The semiconductor device mounted structure as defined in claim 1, wherein

the resin has a two-layer structure of first and second resin sheets, and

the first resin sheet to be placed on the board side is formed smaller in outer shape than the second resin sheet to be placed on the semiconductor device side, and a space adjacent to an outer periphery of the first resin sheet is covered with the second resin sheet, whereby the void portion is formed.

11. The semiconductor device mounted structure as defined in claim 10, wherein the outer shape of the first resin sheet is set generally equal to or smaller than the outer shape of the semiconductor device.

12. The semiconductor device mounted structure as defined in claim 10, wherein a viscosity of a resin material from which the first resin sheet is formed is higher than a viscosity of a resin material from which the second resin sheet is formed.

13. The semiconductor device mounted structure as defined in claim 1, wherein the sealing-bonding use resin is an insulative resin sheet or anisotropic electroconductive resin sheet.

14. A semiconductor device mounting method comprising:

at a position corresponding to an edge portion or its proximity of a semiconductor device mounting area on a board, placing a sealing-connecting use resin on a surface of the board so that a void is formed between the board and the sealing-connecting use resin;

pressing the semiconductor device against the board via the sealing-connecting use resin so that device electrodes of the semiconductor device and board electrodes of the board are connected to each other via bump electrodes, respectively, while the device electrodes, the board electrodes and the bump electrodes, respectively, are sealed by the resin; and

heating the sealing-connecting use resin to expand the void and thereafter curing the resin, whereby a void portion is formed at a position corresponding to an edge portion or its proximity of the semiconductor device in the sealing-connecting use resin and whereby the semiconductor device is mounted onto the board.

15. The semiconductor device mounting method as defined in claim 14, wherein by the placing of the resin on the surface of the board, the void is formed at a corner portion or its proximity of the mounting area, and

by the heating and curing of the sealing-connecting use resin, the void portion is formed at a position corresponding to a corner portion or its proximity of the semiconductor device in the sealing-connecting use resin.

16. The semiconductor device mounting method as defined in claim 15, wherein in the placing of the resin, an inner space of a recess portion previously formed at the corner portion of the semiconductor device mounting area on the board is covered with the resin, whereby the void is formed.

17. The semiconductor device mounting method as defined in claim 16, wherein the recess portion is formed on an upper surface of a recess-portion-forming board electrode which is formed at the corner portion of the semiconductor device mounting area on the board and which is not connected to any of the device electrodes.

18. The semiconductor device mounting method as defined in claim 14, wherein by the placing of the resin on the surface of the board, the void is formed at a position corresponding to a side edge portion or its proximity of the mounting area, and

by the heating and curing of the sealing-connecting use resin, the void portion is formed at a position corresponding to a side edge-line portion or its proximity of the semiconductor device in the sealing-connecting use resin.

19. The semiconductor device mounting method as defined in claim 18, wherein the sealing-connecting use resin is placed on a surface of the board on which a wall member formed from an insulative resin material is placed at a position inner than the side edge-line portion or its proximity of the semiconductor device mounting area, whereby the void is formed at a position corresponding to the side edge-line portion or its proximity of the mounting area, and

a flow of the heated and molten sealing-connecting use resin is suppressed by the wall member, whereby the void portion is formed between an outer peripheral side face of the wall member and the resin.

20. The semiconductor device mounting method as defined in claim 14, wherein in the placing of the resin, which is provided with use of a resin sheet having a two-layer structure of first and second resin sheets, the first resin sheet to be placed on the board side is formed smaller in outer shape than the second resin sheet to be placed on the semiconductor device side, and by placing of the first and second resin sheets on the board, a space adjacent to an outer periphery of the first resin sheet is covered with the second resin sheet, whereby the void is formed.

21. The semiconductor device mounting method as defined in claim 20, wherein in the placing of the resin sheet of the two-layer structure, the first resin sheet whose outer shape is set generally equal to or smaller than the outer shape of the semiconductor device is used.

22. The semiconductor device mounting method as defined in claim 20, wherein a viscosity of a resin material from which the first resin sheet is formed is higher than a viscosity of a resin material from which the second resin sheet is formed.

23. The semiconductor device mounting method as defined in claim 14, wherein as the sealing-bonding use resin, an insulative resin sheet or anisotropic conductive resin sheet is used and placed on the board.

24. A semiconductor device mounting method comprising:

placing a foaming agent at a position corresponding to an edge portion or its proximity of a semiconductor device mounting area on a board, and placing a resin on a surface of the board;

pressing the semiconductor device against the board via the sealing-connecting use resin so that device electrodes of the semiconductor device and board electrodes of the board are connected to each other via bump electrodes, respectively, while the device electrodes, the board electrodes and the bump electrodes, respectively, are sealed by the resin; and

heating the sealing-connecting use resin to make foams expanded by the foaming agent and thereafter curing the resin, whereby a void portion is formed at a position corresponding to an edge portion or its proximity of the semiconductor device in the sealing-connecting use resin and whereby the semiconductor device is mounted onto the board.