Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

• US 20110001542A1
• Filed: 06/18/2010
• Published: 01/06/2011
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Bawell, Shawn, Englekirk, Robert Mark, Greene, Robert W., Ranta, Tero Tapio, Brindle, Christopher N.
• Granted Patent: US 8,669,804 B2
• Time in Patent Office: Days
• US Class Current: 327/382
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Claims

1. A unit cell for a sub-circuit of a digitally tunable capacitor (DTC), the sub-circuit being adapted to be coupled between a first RF terminal and a second RF terminal, the unit cell comprising:

a plurality of stacked switches, the stacked switches proceeding from a first switch closest to the first RF terminal and farthest from the second RF terminal to an n-th switch farthest from the first RF terminal and closest to the second RF terminal, wherein;

the first RF terminal is a terminal through which a voltage source is adapted to be coupled to the unit cell;

the stacked switches comprise a first set of switches close to the first RF terminal and far from the second RF terminal and a second set of switches far from the first RF terminal and close to the second RF terminal, each switch of the first set and second set being coupled in parallel with a compensating capacitor thus providing a compensated capacitance value for that switch when the switch is in an off state, and

each switch of the first set has a corresponding switch of the second set having the same compensated capacitance value.

2. The unit cell of claim 1, wherein the first set of switches consist of switches from the first switch to an i-th switch and the second set of switches consists of switches from an (n−

i+1)-th switch to the n-th switch, i=1, 2, 3, 4 . . . , the n-th switch corresponding to the first switch, the n−

1 switch corresponding to the second switch, and so on.

3. The unit cell of claim 2, wherein capacitance values of the compensating capacitors for the switches of the first set are monotonically descending from a largest capacitance value associated with the first switch to a lowest capacitance value associated with the i-th switch and wherein the capacitance values of the compensating capacitors for the switches of the second set are correspondingly monotonically ascending from a lowest capacitance value associated with the (n−

i+1)-th switch to a largest capacitance value associated with the n-th switch.

4. The unit cell of claim 3, wherein the capacitance values of the compensating capacitors for the switches of the first set are monotonically descending according to a geometric regression and the capacitance values of the compensating capacitors for the switches of the second set are correspondingly monotonically ascending according to a geometric progression.

5. The unit cell of claim 1, wherein the second RF terminal is ground.

6. The unit cell of claim 1, wherein the plurality of stacked switches is coupled in series with one or more metal-insulator-metal (MIM) capacitor or metal-metal (MM) capacitor.

7. The unit cell of claim 1, wherein the sub-circuit is a significant bit sub-circuit.

8. The unit cell of claim 1, wherein each switch of the first set has a corresponding switch of the second set having the same compensated capacitance value and the same compensating capacitor value.

9. An electrical circuit comprising one or more unit cells according to claim 1.

10. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked switches, the stacked switches proceeding from a first switch closest the first terminal and farthest from the second terminal to an n-th switch farthest from the first terminal and closest to the second terminal,

wherein;

the first terminal is a terminal through which a voltage source is adapted to be coupled to the circuit;

the stacked switches comprise a first set of switches close to the first terminal and far from the second terminal and a second set of switches far from the first terminal and close to the second terminal, each switch of the first set and second set being coupled in parallel with a compensating capacitor thus providing a compensated capacitance value for that switch when the switch is in an off state, and

each switch of the first set has a corresponding switch of the second set having the same compensated capacitance value.

11. The circuit of claim 10, wherein the first terminal and the second terminal are RF terminals.

12. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked elements, the stacked elements proceeding from a first element closest the first terminal and farthest from the second terminal to an n-th element farthest from the first terminal and closest to the second terminal,

wherein;

nodes between the elements exhibit parasitic capacitances,

the first terminal is a terminal through which a voltage source is coupled to the circuit;

the stacked elements comprise a first set of elements close to the first terminal and far from the second terminal and a second set of elements far from the first terminal and close to the second terminal, each element of the first set and second set being coupled in parallel with a compensating capacitor, and

each element of the first set has a corresponding element of the second set having the same compensating capacitor value.

13. The circuit of claim 12, wherein the elements are selected between capacitors, resistors, transistors, diodes and inductors.

14. The circuit of claim 12, wherein the first terminal and the second terminal are RF terminals.

15. A circuit coupled between a first RF terminal and a second RF terminal, comprising:

a plurality of stacked elements, the stacked elements proceeding from a first element closest the first RF terminal and farthest from the second RF terminal to an n-th element farthest from the first RF terminal and closest to the second RF terminal,

wherein;

nodes between the elements exhibit parasitic capacitances, and

the first RF terminal is a terminal through which a voltage source is coupled to the circuit,

the circuit further comprising one or more compensation capacitors to compensate the parasitic capacitances, wherein combination between the stacked elements and the compensation capacitors provides a symmetrically compensated plurality of stacked elements with reference to a central node between the elements.

16. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked elements, the stacked elements proceeding from a first element closest the first terminal and farthest from the second terminal to an n-th element farthest from the first terminal and closest to the second terminal,

a plurality of compensating capacitors associated with the stacked elements,

wherein;

nodes between the elements exhibit parasitic capacitances,

the first terminal is a terminal through which a voltage source is coupled to the circuit;

the stacked elements comprise a first set of elements close to the first terminal and far from the second terminal and a second set of elements far from the first terminal and close to the second terminal,

the compensating capacitors comprise a first set of compensating capacitors associated with the first set of elements and a second set of compensating capacitors associated with the second set of elements,

the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first element of the first set of elements, the second capacitor of the first set of capacitors being located in parallel with a series of the first element and a second element of the first set of elements, the third capacitor of the first set of capacitors being located in parallel with a series of the first element, the second element and a third element of the first set of elements and so on, and

the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first element of the second set of elements, the second capacitor of the second set of capacitors being located in parallel with a series of the first element and a second element of the second set of elements, the third capacitor of the second set of capacitors being located in parallel with a series of the first element, the second element and a third element of the second set of elements and so on.

17. The circuit of claim 16, wherein a combination of elements, parasitic capacitances and compensating capacitors at each node of the stack provides a compensated capacitance value for that node, the compensated capacitances being symmetric with respect to a central node of the stack.

18. The circuit of claim 16, wherein the elements are selected between capacitors, resistors, transistors, diodes and inductors.

19. The circuit of claim 16, wherein the first and second terminals are RF terminals.

20. The circuit of claim 16, wherein the compensating capacitors are located on the side of the stacked elements.

21. The circuit of claim 16, wherein the compensating capacitors are located above the stacked elements.

22. The circuit of claim 16, wherein capacitance values of the compensating capacitors of the first and second set of compensating capacitors are monotonically descending from a largest capacitance value of the first compensating capacitor to a lowest capacitance value of the i-th compensating capacitor.

23. The circuit of claim 22, wherein the compensating capacitors of the first and second set are located above or on the side of the stacked elements, each occupying an area which is monotonically descending from a largest area of the first compensating capacitor to a lowest area of the i-th compensating capacitor.

24. A circuit coupled between a first terminal and a second terminal, comprising:

a plurality of stacked switches, the stacked switches proceeding from a first switch closest the first terminal and farthest from the second terminal to an n-th switch farthest from the first terminal and closest to the second terminal,

a plurality of compensating capacitors associated with the stacked switches,

wherein;

nodes between the switches exhibit parasitic capacitances,

the first terminal is a terminal through which a voltage source is adapted to be coupled to the circuit;

the stacked switches comprise a first set of switches close to the first terminal and far from the second terminal and a second set of switches far from the first terminal and close to the second terminal,

the compensating capacitors comprise a first set of compensating capacitors associated with the first set of switches,

the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first switch of the first set of switches, the second capacitor of the first set of capacitors being located in parallel with a series of the first switch and a second switch of the first set of switches, the third capacitor of the first set of capacitors being located in parallel with a series of the first switch, the second switch and a third switch of the first set of switches and so on.

25. The circuit of claim 24, further comprising a second set of compensating capacitors associated with the second set of switches, wherein the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first switch of the second set of switches, the second capacitor of the second set of capacitors being located in parallel with a series of the first switch and a second switch of the first set of switches, the third capacitor of the second set of capacitors being located in parallel with a series of the first switch, the second switch and a third switch of the second set of switches and so on.