SUB-THRESHOLD CMOS TEMPERATURE DETECTOR
First Claim
1. A CMOS temperature detection circuit, comprising:
- a start-up circuit for generating a start-up voltage;
a proportional to absolute temperature (PTAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current;
a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage (VBE) and a PTAT voltage, wherein first and second alarm values are derived from the PTAT voltage; and
a comparator circuit coupled to the voltage generator for comparing the PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results.
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Abstract
A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on the PTAT current generator, and the PTAT current generator uses the sub-threshold characteristics of CMOS to generate the PTAT current. A PTAT voltage generator coupled to the PTAT current generator receives the PTAT current and generates a PTAT voltage and an inverse PTAT voltage (VBE). A comparator circuit coupled to the voltage generator compares the inverse PTAT voltage to first and second alarm limits, which are defined using the generated PTAT voltage, and generates an alarm signal based on the comparison results.
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Citations
20 Claims
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1. A CMOS temperature detection circuit, comprising:
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a start-up circuit for generating a start-up voltage; a proportional to absolute temperature (PTAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current; a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage (VBE) and a PTAT voltage, wherein first and second alarm values are derived from the PTAT voltage; and a comparator circuit coupled to the voltage generator for comparing the PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A CMOS temperature detection circuit, comprising:
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a start-up circuit for generating a start-up voltage, the start-up circuit including; a first PMOS transistor having a source connected to a first power supply; a first NMOS transistor having a drain connected to a drain of the first PMOS transistor at a first node, a source connected to a second power supply, and a gate connected to the second power supply; and a second PMOS transistor having a source connected to the first power supply, and a gate connected to the drains of the first NMOS transistor and the first PMOS transistor at the first node; a proportional to absolute temperature (PTAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current, wherein the PTAT current generator comprises; a third PMOS transistor having a source connected to the first power supply; a fourth PMOS transistor having a source connected to the first power supply and a gate connected to a gate of the third PMOS transistor, wherein the PTAT current is generated at a node between the gates of the third and fourth PMOS transistors; a second NMOS transistor having a drain connected to a drain of the third PMOS transistor, a source connected to the second power supply, and a gate connected to its drain; a third NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the gate of the second NMOS transistor; and a shunt resistor connected between the third NMOS transistor and the second power supply; a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage and a PTAT voltage, wherein first and second alarm values are defined using the PTAT voltage; and a comparator circuit coupled to the voltage generator for comparing the PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results. - View Dependent Claims (15, 16, 17, 18)
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19. A CMOS temperature detection circuit, comprising:
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a start-up circuit for generating a start-up voltage, the start-up circuit including; a first PMOS transistor having a source connected to a first power supply; a first NMOS transistor having a drain connected to a drain of the first PMOS transistor at a first node, a source connected to a second power supply, and a gate connected to the second power supply; and a second PMOS transistor having a source connected to the first power supply, and a gate connected to the drains of the first NMOS transistor and the first PMOS transistor at the first node; a proportional to absolute temperature (PTAT) current generator formed using CMOS technology, coupled to the start-up circuit, for generating a PTAT current, wherein the start-up voltage turns on the PTAT current generator, and wherein the PTAT current generator uses the sub-threshold characteristics of the CMOS technology to generate the PTAT current, wherein the PTAT current generator includes; a third PMOS transistor having a source connected to the first power supply; a fourth PMOS transistor having a source connected to the first power supply and a gate connected to a gate of the third PMOS transistor, wherein the PTAT current is generated at a node between the gates of the third and fourth PMOS transistors; a second NMOS transistor having a drain connected to a drain of the third PMOS transistor, a source connected to the second power supply, and a gate connected to its drain; a third NMOS transistor having a source connected to the second power supply, a drain connected to a drain of the fourth PMOS transistor, and a gate connected to the gate of the second NMOS transistor; and a shunt resistor connected between the third NMOS transistor and the second power supply; a PTAT voltage generator coupled to the PTAT current generator that receives the PTAT current and generates an inverse PTAT voltage and a PTAT voltage, wherein first and second alarm values are derived using the PTAT voltage, wherein the PTAT voltage generator includes; a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors; a sixth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors; a fifth PMOS transistor having a source connected to the first power supply and a gate connected to the gates of the third and fourth PMOS transistors; a first resistor connected between a drain of the fifth PMOS transistor and the second power supply for defining the first alarm value; a second resistor connected between a drain of the sixth PMOS transistor and the second power supply for defining the second alarm value; and a bi-polar junction transistor (BJT) having an emitter connected to a drain of the seventh PMOS transistor, a base connected to the second power supply, and a collector also connected to the second power supply; and a comparator circuit coupled to the voltage generator for comparing the PTAT voltage to the first and second alarm values, respectively, and generating an alarm signal based on the comparison results. - View Dependent Claims (20)
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Specification