DIE-TO-DIE ELECTRICAL ISOLATION IN A SEMICONDUCTOR PACKAGE

• US 20110001587A1
• Filed: 06/17/2010
• Published: 01/06/2011
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Granted Patent: US 8,564,091 B2
• Time in Patent Office: Days
• US Class Current: 333/24.R
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03H 2/00 : Networks using elements or techniques not provided for in groups H03H3/00 - H03H21/00

Abstract

Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die. Other embodiments are also described and claimed.

Claims

1. A semiconductor package comprising:

a first die;

a second die; and

an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die.

2. The semiconductor package of claim 1, wherein the inductor arrangement is configured to inductively transmit signals between the first die and the second die.

3. The semiconductor package of claim 1, wherein the inductor arrangement includes a first inductor circuit comprising:

a first bond wire electrically coupled between a first connector in the first die and a second connector in the second die;

a first interconnect electrically coupled between the second connector in the second die and a third connector in the second die; and

a second bond wire electrically coupled between the third connector in the second die and a fourth connector in the first die.

4. The semiconductor package of claim 3, wherein the second connector, the third connector and the first interconnect are electrically isolated from active circuit components of the second die.

5. The semiconductor package of claim 3, further comprising:

an insulating layer formed between the first interconnect and the active circuit components of the second die.

6. The semiconductor package of claim 3, wherein the inductor arrangement further includes a second inductor circuit comprising:

a third bond wire electrically coupled between a fifth connector in the second die and a sixth connector in the first die;

a second interconnect electrically coupled between the sixth connector in the first die and a seventh connector in the first die, wherein the sixth connector, the seventh connector and the second interconnect are electrically isolated from active circuit components of the first die; and

a fourth bond wire electrically coupled between the seventh connector in the first die and an eighth connector in the second die.

7. The semiconductor package of claim 6, wherein:

the first die is configured to transmit a first signal through the first inductor circuit such that a second signal is inductively generated in the second inductor circuit;

the second signal is proportional to the first signal; and

the second die is configured to receive the second signal.

8. The semiconductor package of claim 7, wherein:

the second die is configured to transmit a third signal through the second inductor circuit such that a fourth signal is inductively generated in the first inductor circuit;

the fourth signal is proportional to the third signal; and

the first die is configured to receive the fourth signal.

9. The semiconductor package of claim 8, wherein:

the first signal is transmitted during a first plurality of time slots;

the third signal is transmitted during a second plurality of time slots; and

the first plurality of time slots and the second plurality of time slots are interleaved.

10. The semiconductor package of claim 8, wherein:

the first signal and the third signal are transmitted substantially simultaneously; and

a first frequency of the first signal is different from a second frequency of the third signal.

11. The semiconductor package of claim 7, wherein a voltage level of the first signal is different from a voltage level of the second signal.

12. The semiconductor package of claim 1, wherein the first die and the second die operate at different voltage levels.

13. The semiconductor package of claim 1, further comprising:

a die frame;

wherein the first die is attached to the die frame using electrically conductive glue such that the first die is electrically coupled to the die frame; and

wherein the second die is attached to the die frame through an electrical isolation layer such that the second die is electrically isolated from the die frame.

14. The semiconductor package of claim 1, further comprising:

a first die frame, wherein the first die is attached to the first die frame; and

a second die frame, wherein the second die is attached to the second die frame.

15. A method of transmitting signals between a first die and a second die included in a semiconductor package, the method comprising:

providing an inductor arrangement that inductively couples the first die and the second die, while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die, wherein the inductor arrangement includes a first inductor circuit and a second inductor circuit;

transmitting a first signal from the first die through the first inductor circuit such that a second signal is inductively generated in the second inductor circuit; and

receiving the second signal in the second die, wherein the second signal is representative of the first signal.

16. The method of claim 15, further comprising:

transmitting a third signal from the second die through the second inductor circuit such that a fourth signal is inductively generated in the first inductor circuit; and

receiving the fourth signal in the first die, wherein the fourth signal is representative of the third signal.

17. The method of claim 16, wherein:

the first signal is transmitted during a first plurality of time slots;

the third signal is transmitted during a second plurality of time slots; and

the first plurality of time slots and the second plurality of time slots are interleaved.

18. The method of claim 16, wherein:

the first signal and the third signal are transmitted substantially simultaneously; and

a first frequency of the first signal is different from a second frequency of the third signal.

19. The method of claim 15, wherein the first signal is a high frequency signal.

20. The method of claim 15, wherein the first die and the second die are attached to a die frame, such that the first die and the second die are not electrically coupled through the die frame.

21. The method of claim 15, wherein:

the first die is attached to a first die frame; and

the second die is attached to a second die frame.