TFT, SHIFT REGISTER, SCANNING SIGNAL LINE DRIVE CIRCUIT, SWITCH CIRCUIT, AND DISPLAY DEVICE

• US 20110001736A1
• Filed: 10/09/2008
• Published: 01/06/2011
• Est. Priority Date: 02/19/2008
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Imai, Hajime, Kitagawa, Hideki, Kikuchi, Tetsuo, Tanaka, Shinya, Kataoka, Yoshiharu
• Granted Patent: US 8,963,152 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02F 2201/124 interdigital
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A distance (d1) from an edge of a first region (R) at places (D) where branch electrodes (4b) extending, which branch off from an electrode line (4a) of a second source/drain electrode (4), start to overlap with a first region (R) to the electrode line (4a) is 5 μm or more. This realizes a TFT including a comb-shaped source/drain structure that enables easy repair of a source-drain leakage.

Claims

1. A TFT comprising a gate electrode, a first source/drain electrode, and a second source/drain electrode, one of the first source/drain electrode and the second source/drain electrode being a source electrode and the other being a drain electrode,

the TFT including an i layer and a stack in which an n⁺ layer is stacked on the i layer, the i layer and the stack being formed from a semiconductor material and disposed above the gate electrode but with a dielectric layer under the i layer and the stack in a layer-thickness direction,

the first source/drain electrode being disposed on the n⁺ layer in a first region, the first region being a panel in-plane region where the i layer is provided,

the second source/drain electrode including an electrode line provided outside the first region and a plurality of branch electrodes branching off and extending from the electrode line,

the branch electrodes extending from the electrode line onto the n⁺ layer in the first region,

the i layer having a pattern provided between the first source/drain electrode and the branch electrodes in the first region in a panel in-plane direction, the pattern including no n⁺ layer in the first region,

wherein:

when the gate electrode is seen in the layer-thickness direction, an edge of the first region at first places where the branch electrodes extending start to overlap with the first region is (i) nearer to the electrode line than an edge of the gate electrode at second places where the branch electrodes extending start to overlap with a region of the gate electrode;

or (ii) in a same position as the edge of the gate electrode at the second places; and

a first distance from the edge of the first region at the first places to the electrode line is 5 μ

m or more.

2. The TFT according to claim 1, wherein:

the first distance is 10 μ

m or less.

3. The TFT according to claim 1, wherein:

the branch electrode is provided with a cutout narrowing a line width thereof,

the cutout being provided on one side or both sides of the branch electrode in a width direction thereof at a part immediately in front of the first place.

7. The TFT according to claim 1, wherein:

the electrode line is provided with a cutout narrowing a line width thereof,

the cutout being provided on one side or both sides of branching points where the branch electrodes branch off from the electrode line.

8. The TFT according to claim 1, wherein:

the semiconductor material is amorphous silicon.

9. The TFT according to claim 1, wherein:

the semiconductor material is microcrystal silicon.

10. A shift register including a plurality of stages composed of transistors, wherein:

at least one of the transistors is a TFT according claim 1.

11. A scanning signal line drive circuit including a shift register according to claim 10, wherein:

the shift register is used to generate a scanning signal for a display device.

12. The scanning signal line drive circuit according to claim 11, wherein:

the TFT is an output transistor outputting the scanning signal.

13. A display device including a scanning signal line drive circuit according to claim 11.

14. The display device according to claim 13, wherein:

the scanning signal line drive circuit is formed on a display panel so as to be monolithically integrated with a display region.

15. A switch circuit including a plurality of TFTs according to claim 1, wherein:

the TFTs are provided correspondingly for a plurality of paths, respectively, and

the TFTs serving as switches via which each of outputs of a data signal line drive circuit is connected to the respective paths in a branched manner.

16. The switch circuit according to claim 15, wherein:

when seen in a layer-thickness direction, each of the TFTs serving as the switches has a rectangular region whose longer side is in parallel with an extending direction of data signal lines serving as the paths.

17. The switch circuit according to claim 15, wherein:

when seen in a layer-thickness direction, each of the TFTs serving as the switches has a rectangular region whose longer side is orthogonal to an extending direction of data signal lines serving as the paths.

18. A display device including a switch circuit and a data signal line drive circuit according to claim 15, wherein:

a plurality of paths are data signal lines.

19. The display device according to claim 18, wherein:

the display device is driven such that, with respect to each of the outputs, the switches are conducted in a time-sharing manner during a horizontal period.

20. The display device according to claim 18, wherein:

the switch circuit is formed on a display panel so as to be monolithically integrated with a display region.

21. A display device including:

a scanning signal line drive circuit including a shift register used to generate a scanning signal for the display device, the shift register having a plurality of stages composed of transistors, wherein at least one of the transistors is a TFT comprising a gate electrode, a first source/drain electrode, and a second source/drain electrode, one of the first source/drain electrode and the second source/drain electrode being a source electrode and the other being a drain electrode,

the TFT including an i layer and a stack in which an n⁺ layer is stacked on the i layer, the i layer and the stack being formed from a semiconductor material and disposed above the gate electrode but with a dielectric layer under the i layer and the stack in a layer-thickness direction,

the first source/drain electrode being disposed on the n⁺ layer in a first region, the first region being a panel in-plane region where the i layer is provided,

the second source/drain electrode including an electrode line provided outside the first region and a plurality of branch electrodes branching off and extending from the electrode line,

the branch electrodes extending from the electrode line onto the n⁺ layer in the first region,

the i layer having a pattern provided between the first source/drain electrode and the branch electrodes in the first region in a panel in-plane direction, the pattern including no n⁺ layer in the first region,

wherein;

when the gate electrode is seen in the layer-thickness direction, an edge of the first region at first places where the branch electrodes extending start to overlap with the first region is (i) nearer to the electrode line than an edge of the gate electrode at second places where the branch electrodes extending start to overlap with a region of the gate electrode;

or (ii) in a same position as the edge of the gate electrode at the second places; and

a first distance from the edge of the first region at the first places to the electrode line is 5 μ

m or more; and

a switch circuit and a data signal line drive circuit according to claim 15,

a plurality of paths being data signal lines.

22. The display device according to claim 21, wherein:

at least one of the scanning signal line drive circuit and the switch circuit is formed on a display panel so as to be monolithically integrated with a display region.

23. A display device, wherein:

a TFT according to claim 1 is formed on a display panel so as to be monolithically integrated with a display region.

4. A TFT comprising a gate electrode, a first source/drain electrode, and a second source/drain electrode, one of the first source/drain electrode and the second source/drain electrode being a source electrode and the other being a drain electrode,

the TFT including an i layer and a stack in which an n⁺ layer is stacked on the i layer, the i layer and the stack being formed from a semiconductor material and disposed above the gate electrode but with a dielectric layer under the i layer and the stack in a layer-thickness direction,

the first source/drain electrode being disposed on the n⁺ layer in a first region, the first region being a panel in-plane region where the i layer is provided,

the second source/drain electrode including an electrode line provided outside the first region and a plurality of branch electrodes branching off and extending from the electrode line,

the branch electrodes extending from the electrode line onto the n⁺ layer in the first region,

the i layer having a pattern provided between the first source/drain electrode and the branch electrodes in the first region in a panel in-plane direction, the pattern including no n⁺ layer in the first region,

wherein:

when the gate electrode is seen in the layer-thickness direction, an edge of the first region at first places where the branch electrodes extending start to overlap with the first region is more away from the electrode line than an edge of the gate electrode at second places where the branch electrodes extending start to overlap with a region of the gate electrode; and

a second distance from the edge of the gate electrode at the second places to the electrode line is 5 μ

m or more.

5. The TFT according to claim 4, wherein:

the second distance is 10 μ

m or less.

6. The TFT according to claim 4, wherein:

the branch electrode is provided with a cutout narrowing a line width thereof,

the cutout being provided on one side or both sides of the branch electrode in a width direction thereof at a part immediately in front of the second place.