METHOD AND APPARATUS FOR USE IN DIGITALLY TUNING A CAPACITOR IN AN INTEGRATED CIRCUIT DEVICE
First Claim
1. A digitally tuned capacitor (DTC) for use in an integrated circuit device, comprising:
- (a) a first RF terminal;
(b) a second RF terminal;
(c) a control word input capable of receiving a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB), and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals;
(d) a plurality of significant bit sub-circuits coupled in parallel between the first and second RF terminals, wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises;
(i) at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with a capacitor;
wherein switching operation of the stacked switches is controlled by the associated and corresponding bit of the control word, and wherein the LSB sub-circuit comprises one unit cell, and each next significant bit sub-circuit comprises x times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, wherein x is determined by a selected weighting coding scheme used to weight the sub-circuits, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;
and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.
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Accused Products
Abstract
A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an FW+ terminal and the second terminal comprises an RF terminal. In accordance with some embodiments, the DTCs comprises a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second FW terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.
299 Citations
64 Claims
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1. A digitally tuned capacitor (DTC) for use in an integrated circuit device, comprising:
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(a) a first RF terminal; (b) a second RF terminal; (c) a control word input capable of receiving a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB), and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals; (d) a plurality of significant bit sub-circuits coupled in parallel between the first and second RF terminals, wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises; (i) at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with a capacitor;
wherein switching operation of the stacked switches is controlled by the associated and corresponding bit of the control word, and wherein the LSB sub-circuit comprises one unit cell, and each next significant bit sub-circuit comprises x times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, wherein x is determined by a selected weighting coding scheme used to weight the sub-circuits, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal;and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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9. The DTC of claim 4, wherein the unit cell further comprises a plurality of gate resistors RG having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding significant bit of the digital control word, and wherein the unit cell further comprises a plurality of drain-to-source resistors RDS coupled across the drain and sources of each FET of the FET stack.
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10. The DTC of claim 4, wherein the significant bit sub-circuits further comprise a plurality of gate resistors RG having first terminals coupled to gates of associated and corresponding FETs of the FET stack and second terminals coupled to the associated and corresponding significant bit of the digital control word, and wherein the sub-circuits further comprise a plurality of drain-to-source resistors RDS coupled across the drain and source of each FET of the FET stack, and wherein the resistance of the gate resistors RG/2 of each next significant bit sub-circuit is ½
- that of the resistance of the gate resistors RG of its associated and corresponding previous less significant bit sub-circuit, and wherein the resistance of the drain-to-source resistors RDS/2 of each next significant bit sub-circuit is ½
that of the resistance of the drain to source resistors RDS of its associated and corresponding previous less significant bit sub-circuit.
- that of the resistance of the gate resistors RG of its associated and corresponding previous less significant bit sub-circuit, and wherein the resistance of the drain-to-source resistors RDS/2 of each next significant bit sub-circuit is ½
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11. The DTC of claim 10, wherein the integrated circuit die area 10 by the DTC of claim 10 is significantly less than the integrated circuit die area occupied by the DTC of claim 9.
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12. The DTC of claim 3, wherein the thermometer weighting coding scheme results in the DTC having 2b possible capacitance tuning states using 2b-1 identical unit cells, and wherein a capacitance differential between two adjacent capacitive tuning states of the control word are identical.
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13. The DTC of claim 4, wherein a switching time of the FET stack is equal to RG*CGATE, wherein RG comprises a gate resistance of the FET stack and CGATE comprises a gate capacitance of the FET stack, and wherein the switching time is constant across all FETs of the DTC.
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14. The DTC of claim 4, wherein the unit cell has a quality factor (Q), and wherein the Q-factor of the unit cell is dominated by a relationship between an ON resistance RON of the FET stack when the FET stack is turned ON and capacitance of the MIM capacitor (CMIM), and wherein constant Q-factors are maintained across of all of the DTC sub-circuits because the relationship between RON and CMIM remains constant across the entire DTC.
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15. The DTC of claim 14, wherein the DTC is implemented in accordance with the following idealized design equations (Equations 1-4):
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16. The DTC of claim 9, wherein the unit cell has a quality factor when the FET stack is turned ON (ON state Q-factor QON) and a quality factor when the FET stack is turned OFF (OFF state Q-factor QOFF), and wherein QON is proportional to 1/f wherein f comprises a frequency of a signal applied to the DTC first and second RF terminals.
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17. The DTC of claim 16, wherein the first RF terminal is coupled to an RF+ load and the second RF terminal is coupled to ground, and wherein the QON of the unit cell is determined in accordance with the following mathematical expression:
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18. The DTC of claim 16, wherein the first RF terminal is coupled to ground and the second RF terminal is coupled to an RF−
- load, and wherein the QON of the unit cell is determined in accordance with the following mathematical expression;
- load, and wherein the QON of the unit cell is determined in accordance with the following mathematical expression;
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19. The DTC of claim 17, wherein the QOFF of the unit cell is determined in accordance with the following mathematical expression:
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20. The DTC of claim 18, wherein the QOFF of the unit cell is determined in accordance with the following mathematical expression:
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21. The DTC of claim 2, wherein the DTC is implemented in accordance with a combination of both binary weighting and thermometer weighting codes.
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22. The DTC of claim 4, wherein n=1.
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23. The DTC of claim 4, wherein the significance of the digital control word bits are arranged in ascending order from an LSB bb-1 through an MSB b0.
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24. The DTC of claim 4, wherein the significance of the digital control word bits are arranged in descending order from an MSB bb-1 through an LSB b0.
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25. The DTC of claim 4, wherein the unit cell FET stack has a width and is sized in accordance with a number y fingers of the FET stack, and wherein the width and number y of fingers are adjusted to provide a selected desirable size of the DTC.
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26. The DTC of claim 4, wherein the MIM capacitor comprises one or more stacked capacitors, wherein the one or more stacked capacitors are selected to optimize the power handling capability of the DTC.
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27. The DTC of claim 4, wherein the FETs comprise Accumulated Charge Control (ACC) SOI MOSFETs.
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28. The DTC of claim 4, wherein the DTC is implemented using any of the following processing technologies:
- gallium-arsenide (GaAs), Silicon-on-insulator (SOD, silicon-on-sapphire (SOS).
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29. The DTC of claim 1, wherein the plurality of stacked switches comprise electro-Mechanical Systems (MEMS) switches.
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30. The DTC of claim 1, wherein the plurality of stacked switches comprise laterally diffused metal oxide semiconductor (LDMOS) transistors.
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31. The DTC of claim 4, wherein MIM capacitor is integrated on an integrated circuit die wherein the DTC is implemented.
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32. The DTC of claim 4, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying a selected negative voltage to the gates of the FETs in the FET stack.
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33. The DTC of claim 4, wherein the digital control word bits selectively turn the FET stack ON by applying a selected positive voltage to the gates of the FETs in the FET stack, and wherein the bits turn the FET stack OFF by applying 0 volts to the gates of the FETs in the FET stack.
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34. The DTC of claim 4, further including a fixed capacitor coupled in parallel between the first and second RF terminals.
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35. The DTC of claim 34, wherein the included fixed capacitor is optimized to reduce an amount of integrated circuit die space required to implement the DTC.
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36. The DTC of claim 34, wherein the included fixed capacitor is optimized to reduce a tuning ratio of the DTC.
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37. The DTC of claim 4, wherein the DTC is implemented in an integrated circuit device, and wherein the integrated circuit device contains one or more additional DTCs as set forth in claim 4, and wherein one or more of the RF terminals are coupled together with one or more of the additional DTCs implemented in the integrated circuit device.
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38. The DTC of claim 37, wherein the DTC is coupled with the one or more of the additional DTCs in a series configuration.
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39. The DTC of claim 37, wherein the DTC is coupled with the one or more of the additional DTCs in a parallel configuration.
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40. The DTC of claim 37, wherein the DTC is uncoupled and thereby isolated from the one or more additional DTCs contained in the integrated circuit device.
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41. A digitally tuned capacitor (DTC) for use in an integrated circuit device, comprising:
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(a) a first RF terminal; (b) a second RF terminal; (c) a control word input capable of receiving a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB), and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals; (d) a plurality of significant bit sub-circuits coupled in parallel between the first and second RF terminals, wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises at least one unit cell and wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the significant bit sub-circuits. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
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64. A method of digitally tuning a capacitor in an integrated circuit device, comprising:
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(a) establishing electrical communication with a first RF terminal; (b) establishing electrical communication with a second RF terminal; (c) receiving a digital control word having a selected plurality of b bits, wherein the plurality of b digital control word bits are ordered in significance from a least significant bit (LSB) to a most significant bit (MSB); and (d) selectively controlling a capacitance applied between the first and second RF terminals; wherein the capacitance applied between the first and second RF terminals is controlled by coupling a plurality of significant bit sub-circuits in parallel between the first and second RF terminals, and wherein the plurality of significant bit sub-circuits are ordered in significance from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit, and wherein each significant bit sub-circuit is coupled to an associated and corresponding significant bit of the digital control word, in a one-to-one relationship, and wherein each significant bit sub-circuit comprises at least one unit cell, wherein the unit cell comprises a plurality of stacked switches coupled in series with a capacitor;
wherein switching operation of the stacked switches is controlled by the associated and corresponding bit of the control word, and wherein the LSB sub-circuit comprises one unit cell, and each next significant bit sub-circuit comprises x times the number of instantiations of unit cells used in implementing its associated and corresponding previous less significant bit sub-circuit, wherein x is determined by a selected weighting coding scheme used to weight the sub-circuits, and wherein all of the unit cells of each sub-circuit are coupled together in parallel having a first node coupled to the first RF terminal and a second node coupled to the second RF terminal; and
wherein the digital control word selectively controls a capacitance applied between the first and second RF terminals by selectively controlling switching operation of the stacked switches, wherein capacitance applied between the first and second RF terminals by a selected sub-circuit is controlled by selectively turning ON stacked switches of the selected sub-circuit.
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Specification