Binary Logic Utilizing MEMS Devices

• US 20110002168A1
• Filed: 06/18/2010
• Published: 01/06/2011
• Est. Priority Date: 07/01/2009
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Cavendish Kinetics Inc (Qorvo, Inc.)
• Inventors: Schepens, Cornelius Petrus Elisabeth, Khieu, Cong Quoc, Van Kampen, Robertus Petrus
• Granted Patent: US 8,203,880 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
• CPC Class Codes: H03K 19/02 using specified components H03K19/0005 - H03K19/0021, H03K19/003 - H03K19/0175 take precedence

Abstract

Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the devices may be used for logic applications. MEMS switches may be used in devices such as FPGAs, NAND devices, nvSRAM devices, AMS chips and general memory logic devices. The benefit of utilizing MEMS devices in place of transistors is that the transistors utilize more space on the chip. Additionally, the MEMS devices can be formed in the BEOL without having any negative impacts on the FEOL or necessitating the use of additional layers within the chip.

Claims

1. A nvSRAM device, comprising:

at least one micro electromechanical device having a first contact electrode, a second contact electrode, a first pull-in electrode, a second pull-in electrode, and a rocker electrode movable from a position in contact with the first contact electrode to a position spaced from both the first contact electrode and the second contact electrode to a position in contact with the second contact electrode;

at least one transistor;

a plurality of bit lines;

a VddRow line;

a word line;

a store line;

a restore line; and

a Vss line.

2. The nvSRAM device of claim 1, wherein the at least one transistor comprises:

a first transistor comprising a first source electrode, a first drain electrode and a first gate electrode;

a second transistor comprising a second source electrode, a second drain electrode and a second gate electrode;

a third transistor comprising a third source electrode, a third drain electrode and a third gate electrode;

a fourth transistor comprising a fourth source electrode, a fourth drain electrode and a fourth gate electrode;

a fifth transistor comprising a fifth source electrode, a fifth drain electrode and a fifth gate electrode;

a sixth transistor comprising a sixth source electrode, a sixth drain electrode and a sixth gate electrode;

a seventh transistor comprising a seventh source electrode, a seventh drain electrode and a seventh gate electrode; and

an eighth transistor comprising an eighth source electrode, an eighth drain electrode and an eighth gate electrode.

3. The nvSRAM device of claim 2, wherein the seventh source electrode, the third source electrode, the fourth source electrode and the second pull-in electrode are each coupled to the Vss line.

4. The nvSRAM device of claim 2, wherein the seventh gate electrode and the eighth gate electrode are each coupled to the Restore line.

5. The nvSRAM device of claim 2, wherein the first pull-in electrode is coupled to the Store line.

6. The nvSRAM device of claim 2, wherein the fifth gate electrode and the sixth gate electrode are each coupled to the word line.

7. The nvSRAM device of claim 2, wherein the first source electrode, the second source electrode and the eighth source electrode are each coupled to the VddRow line.

8. The nvSRAM device of claim 2, wherein the fifth source electrode and the sixth source electrode are each coupled to separate bit lines.

9. The nvSRAM device of claim 2, wherein the fifth drain electrode, the rocker electrode, the first drain electrode, the third drain electrode, the second gate electrode and the fourth gate electrode are all coupled together.

10. The nvSRAM device of claim 2, wherein the first gate electrode, the third gate electrode, the second drain electrode, the fourth drain electrode and the sixth drain electrode are all coupled together.

11. The nvSRAM device of claim 2, wherein the seventh drain electrode is coupled to the first contact electrode and wherein the eighth drain electrode is coupled to the second contact electrode.

12. The nvSRAM device of claim 2, wherein the plurality of bit lines are parallel to each other and perpendicular to the VddRow line, the word line, the Store line, the Restore line and the Vss line.

13. A NAND-based non-volatile memory architecture, comprising:

a first micro electromechanical device having a first pull-up electrode, a first pull-in electrode, a first contact electrode and a first cantilever electrode movable between a position in contact with the first contact electrode and a position spaced from the first contact electrode;

a second micro electromechanical device having a second pull-up electrode, a second pull-in electrode, a second contact electrode and a second cantilever electrode movable between a position in contact with the second contact electrode and a position spaced from the second contact electrode, the second cantilever electrode is coupled to the first contact electrode;

a first word line coupled to the first pull-in electrode;

a second word line coupled to the second pull-in electrode;

a Vss line coupled to the first cantilever electrode; and

a transistor coupled to the second micro electromechanical device.

14. The NAND-based non-volatile memory architecture of claim 13, wherein the transistor comprises a drain electrode coupled to the second contact electrode, a gate electrode and a source electrode.

15. The NAND-based non-volatile memory architecture of claim 14, further comprising:

a bit select line coupled to the gate electrode; and

a bit line coupled to the source electrode.

16. The NAND-based non-volatile memory architecture of claim 14, further comprising a data line coupled to the first pull-up electrode and the second pull-up electrode.

17. A micro electromechanical field programmable logic array, comprising:

a first bit line;

a first block select line;

a first erase column line;

a first erase row line;

a first data line;

a first data select line;

a first transistor having a first source electrode coupled to the bit line, a first drain electrode and a first gate electrode coupled to the block select line;

a second transistor having a second source electrode coupled to the erase column line, a second drain electrode and a second gate electrode coupled to the block select line;

a third transistor having a third source electrode coupled to the data line, a third drain electrode and a third gate electrode coupled to the data select line;

a fourth transistor having a fourth source electrode coupled to the erase row line, a fourth drain electrode and a fourth gate electrode coupled to the data select line;

a first micro electromechanical device having a first contact electrode coupled to both the first drain electrode and the third drain electrode, a first pull-in electrode, a first pull-up electrode coupled to the second drain electrode and a first cantilever electrode movable between a position in contact with the first contact electrode and a position spaced form the first contact electrode; and

a second micro electromechanical device having a second contact electrode, a second pull-in electrode coupled to the first drain electrode and the third drain electrode, a third contact electrode lying in substantially the same plane as the second contact electrode coupled to the fourth drain electrode, and a first rocker electrode movable between positions in contact with the second contact electrode, in contact with the third contact electrode, and spaced from both the second contact electrode and the third contact electrode.

18. The micro electromechanical field programmable logic array of claim 17, further comprising:

a second erase row line;

a second data line;

a fifth transistor having a fifth source electrode coupled to the second data line, a fifth drain electrode and a fifth gate electrode coupled to the data select line;

a sixth transistor having a sixth source electrode coupled to the second erase data line, a sixth drain electrode and a sixth gate electrode coupled to the data select line;

a third micro electromechanical element having a fourth contact electrode coupled to the first cantilever electrode and the fifth drain electrode, a third pull-in electrode, a third pull-up electrode coupled with the second drain electrode, and a second cantilever electrode movable between a position in contact with the fourth contact electrode and a position spaced from the fourth contact electrode;

a fourth micro electromechanical element having a fifth contact electrode, a fourth pull-in electrode coupled with the fifth drain electrode, a sixth contact electrode coupled with the sixth drain electrode, and a second rocker electrode movable between positions in contact with the fifth contact electrode, in contact with the sixth contact electrode, and spaced from both the fifth contact electrode and the sixth contact electrode.

19. The micro electromechanical field programmable logic array of claim 18, further comprising:

a second bit line;

a second erase column line;

a seventh transistor having a seventh source electrode coupled to the second erase column line, a seventh drain electrode and a seventh gate electrode coupled to the block select line;

an eighth transistor having an eighth source electrode coupled to the second bit line, an eighth drain electrode and an eighth gate electrode coupled to the block select line;

a fifth micro electromechanical element having a seventh contact electrode coupled with the eighth drain electrode and the first rocker electrode, a fifth pull-in electrode, a fifth pull-up electrode coupled with the seventh drain electrode, and a fifth cantilever electrode coupled to the second rocker electrode and movable between a position in contact with the seventh contact electrode and a position spaced form the seventh contact electrode; and

a sixth micro electromechanical element having an eighth contact electrode, a sixth pull-in electrode coupled to the first rocker electrode, the eighth drain electrode and the seventh contact electrode, the sixth micro electromechanical element also having a ninth contact electrode and a third rocker electrode movable between positions in contact with the eighth contact electrode, in contact with the ninth contact electrode, and spaced from both the eighth contact electrode and the ninth contact electrode.

20. The micro electromechanical field programmable logic array of claim 17, further comprising:

a second bit line;

a second erase column line;

a fifth transistor having a fifth source electrode coupled to the second erase column line, a fifth drain electrode and a fifth gate electrode coupled to the block select line;

a sixth transistor having an sixth source electrode coupled to the second bit line, a sixth drain electrode and a sixth gate electrode coupled to the block select line;

a third micro electromechanical element having a fourth contact electrode coupled to the first rocker electrode and the sixth drain electrode, a third pull-in electrode, a third pull-up electrode coupled with the fifth drain electrode, and a second cantilever electrode movable between a position in contact with the fourth contact electrode and a position spaced from the fourth contact electrode;

a fourth micro electromechanical element having a fifth contact electrode, a fourth pull-in electrode coupled with the sixth drain electrode, a sixth contact electrode coupled with the fourth drain electrode, and a second rocker electrode movable between positions in contact with the fifth contact electrode, in contact with the sixth contact electrode, and spaced from both the fifth contact electrode and the sixth contact electrode.