Bad Column Management with Bit Information in Non-Volatile Memory Systems

• US 20110002169A1
• Filed: 07/06/2009
• Published: 01/06/2011
• Est. Priority Date: 07/06/2009
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Kim, Kwang-ho, Bottelli, Aldo, Tsai, Frank W., Li, Yan
• Application Number:
  US12/498,220
• Publication Number:
  US 20110002169A1
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.

Claims

1. A non-volatile memory circuit, comprising:

an array of non-volatile memory cells formed along columns of multiple bits, the columns including a plurality of regular columns and one or more redundancy columns, and

a plurality of latches, each corresponding to one of the regular columns and having a bit whose value indicates if the corresponding column is defective,

the memory circuit storing a column redundancy data table whose contents indicate for each redundancy column whether the redundancy column is being used and, for redundancy columns that are being used, a defective regular column to which it corresponds and the bits therein which are defective,

wherein the memory circuit stores data corresponding to the defective bits of defective regular columns in the redundancy column portion.

2. The non-volatile memory circuit of claim 1, wherein each column corresponds to a byte of data.

3. The non-volatile memory circuit of claim 1, wherein the content of the column redundancy data table further indicate for each redundancy column whether the redundancy column is defective.

4. The non-volatile memory circuit of claim 1, wherein the content of the column redundancy data table and the value of the plurality of latches are determined in a test process.

5. The non-volatile memory circuit of claim 1, wherein the memory circuit stores multiple copies of the column redundancy data table.

6. The non-volatile memory circuit of claim 1, wherein the memory circuit further stores the column redundancy data table in complementary form.

7. The non-volatile memory circuit of claim 1, wherein regular columns whose corresponding latch value indicates the regular column is defective and where the column redundancy data table indicates that less than all of the bits therein are defective are used to store valid data in the non-defective bits thereof.

8. The non-volatile memory circuit of claim 1, further comprising:

data latch circuitry connectable to the redundancy columns and responsive to the column redundancy data table contents, whereby the data corresponding to the defective bits of defective regular columns are packed into a compacted form for storage in the redundancy column portion in a write operation and unpacked in a read operation.

9. The non-volatile memory circuit of claim 8, wherein the data corresponding to the defective bits of defective regular columns are packed and unpacked in multi-bit groups.

10. The non-volatile memory circuit of claim 1, wherein the contents of the column redundancy data table further includes a failure mode for the defective regular columns.

11. A method of operating a non-volatile memory circuit, the memory circuit including an array of non-volatile memory cells formed along columns of multiple bits and having a latch associated with each of the columns whose value indicates if the corresponding column has a defect, the method comprising,

performing a write operation to concurrently program a plurality of memory cells on a corresponding plurality of columns, including one or more columns having an associated latch whose value indicates the corresponding column has a defect;

determining the number of the plurality of concurrently programmed memory cells that were not successfully programmed in the write operation, wherein the columns whose latch values indicate the column has a defect are not counted in the determining; and

determining whether the number of cells that were not successfully been programmed during the write operation is acceptable.

12. The method of claim 11, wherein the write operation includes a plurality of alternating pulse and verify operations for all of the cells on which the write operation is being performed, with cells that verify as correctly programmed are locked out from further pulses.

13. The method of claim 11, wherein the number of cells acceptable as not successfully programmed is a predetermined value based on the error correction code capabilities of the memory system of which the memory circuit is a part.

14. The method of claim 11, further comprising:

prior to said programming operation, determining for each of the one or more columns having an associated latch whose value indicates the corresponding column has a defect if the cell to be programmed in the corresponding column is defective; and

in response to determining that the cell to be programmed in the corresponding column is defective, saving the data to programmed therein to a redundancy area of the memory array.

15. The method of claim 14, wherein said determining is based upon a column redundancy data table stored the non-volatile memory circuit whose contents indicate which bits are defective for columns whose associated latch whose value indicates the corresponding column has a defect.

16. A method of operating a non-volatile memory circuit having an array of non-volatile memory cells formed along columns of multiple bits, the columns including a plurality of regular columns and one or more redundancy columns, the method comprising:

performing a plurality of column test operations to determine which columns are defective and the individual bits therein which are defective, each of the column tests including;

writing and reading back an externally supplied data pattern to the columns; and

comparing the externally supplied data pattern as read back with an expected data pattern,

wherein said column test operation are performed by circuitry on the memory circuit and each of the column tests uses a different data pattern;

recording addresses of any of the regular columns determined defective and the individual bits therein which are determined defective in a column redundancy data table stored on the memory circuit; and

for any of the regular columns determined defective, setting a latch associated therewith to a value indicating that the associated column is defective.

17. The method of claim 16, further comprising:

for any of the redundant columns determined defective, setting corresponding flag values in the column redundancy data table.

18. The method of claim 16, wherein the column test operations are executed by a state machine on the memory circuit.

19. The method of claim 16, wherein the recording addresses of any of the regular columns determined defective and the individual bits therein which are determined defective, includes temporarily storing the results of said comparing on another array of the memory circuit.

20. The method of claim 16, wherein the recording addresses of any of the regular columns determined defective and the individual bits therein which are determined defective, includes storing multiple copies of the column redundancy data table on the memory circuit.

21. The method of claim 16, wherein the column test operations further include:

determining a failure mode for the regular columns determined defective; and

recording the failure mode in the column redundancy data table for the regular columns determined defective.

22. A method of operating a non-volatile memory circuit having an array of non-volatile memory cells formed along columns of multiple bits, the columns including a plurality of regular columns and one or more redundancy columns, the method comprising:

storing on the memory circuit a column redundancy data table whose contents indicate for each redundancy column whether the redundancy column is being used and, for redundancy columns that are being used, a defective regular column to which it corresponds and the bits therein which are defective;

receiving a set of data to program into the memory array;

determining the elements of the set of data assigned to be programmed to defective bits of defective regular columns based upon the column redundancy circuit data table;

storing the elements of the set of data determined to be assigned to be programmed to defective bits of defective columns in peripheral latch circuits on the memory circuit;

storing the set of data into programming latches for the memory array;

performing a programming operation into the regular columns of the memory array from the programming latches; and

programming the elements of the data set stored in the peripheral latches into the redundancy columns.

23. The method of claim 22, further comprising:

prior to programming the elements of the data set stored in the peripheral latches into the redundancy columns, performing a packing operation on the memory circuit for the elements of the set of data determined to be assigned to be programmed to defective bits of defective columns, whereby elements of data assigned to be programmed to more than one regular column are programmed into a single redundant column.

24. The method of claim 23, wherein said packing operation includes a plurality of sub-operations, each performing a packing operation on a subset of the set of data determined to be assigned to be programmed to defective bits of defective columns.

25. The method of claim 22, wherein the contents of the column redundancy data table further includes a failure mode for the defective regular columns.