VERTICAL NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME DEVICE, AND ELECTRIC-ELECTRONIC SYSTEM HAVING THE SAME DEVICE
First Claim
Patent Images
1. A vertical non-volatile memory device comprising:
- cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate;
impurity regions formed on second portions of the semiconductor substrate between the cell string units;
conductive lines formed on the impurity regions; and
spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.
-
Citations
20 Claims
-
1. A vertical non-volatile memory device comprising:
-
cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate; impurity regions formed on second portions of the semiconductor substrate between the cell string units; conductive lines formed on the impurity regions; and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 19)
-
-
12. A vertical non-volatile memory device comprising:
-
a semiconductor substrate including a cell region and a peripheral region; cell string units that are formed on first portions within the cell region and are vertically arranged with respect to a surface of the semiconductor substrate; impurity regions formed on second portions between the cell string units within the cell region; and conductive lines formed on the impurity regions, wherein the bottom surfaces of the gate dielectric layers of the bottommost selecting transistors in the cell string units are located lower than the top surface of the semiconductor substrate in the peripheral region. - View Dependent Claims (13, 14, 15, 16, 17, 18)
-
-
20-41. -41. (canceled)
Specification