VERTICAL NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME DEVICE, AND ELECTRIC-ELECTRONIC SYSTEM HAVING THE SAME DEVICE

• US 20110002178A1
• Filed: 06/17/2010
• Published: 01/06/2011
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Han-soo, Cho, Won-seok, Hwang, Sung-min, Jang, Jae-hoon
• Granted Patent: US 8,879,321 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Claims

1. A vertical non-volatile memory device comprising:

cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate;

impurity regions formed on second portions of the semiconductor substrate between the cell string units;

conductive lines formed on the impurity regions; and

spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

2. The vertical non-volatile memory device of claim 1, wherein each of the cell string units comprises selecting transistors and a plurality of memory cell transistors arranged between the selecting transistors, wherein

channel layers are formed to contact the first portions and are vertical to the surface of the semiconductor substrate, and wherein

the selecting transistors and the plurality of memory cell transistors are arranged on the sidewalls of the channel layers.

3. The vertical non-volatile memory device of claim 1, further comprising:

insulation pillars that are formed on the centers of the first portions and vertical to the surface of the semiconductor substrate, wherein

the cell string units comprises,

channel layers that surround the bottom surfaces and the sidewalls of the insulation pillars and contact the first portions of the semiconductor substrate,

gates of selecting transistors that are arranged on the channel layers formed on two opposite sidewalls of each of the insulation pillars and are vertically stacked with respect to the surface of the semiconductor substrate, and

gates of memory cell transistors that are arranged between the gates of the selecting transistors.

4. The vertical non-volatile memory device of claim 3, wherein the conductive lines are formed to be located lower than bottom surfaces of the bottommost gates from among the gates of the memory cell transistors.

5. The vertical non-volatile memory device of claim 1, wherein the spacers are formed on the entire sidewalls of the cells string units, and wherein

the conductive lines are formed in the entire gaps between the spacers or formed in a part of the gaps between the spacers.

6. The vertical non-volatile memory device of claim 1, wherein the spacers are formed on a part of the sidewalls of the cell string units, and wherein

the conductive lines are formed between the spacers.

7. The vertical non-volatile memory device of claim 6, wherein an insulation layer is formed on the conductive lines and the spacers.

8. The vertical non-volatile memory device of claim 1, further comprising:

conductive signal lines on the cell string units.

9. The vertical non-volatile memory device of claim 1, wherein each of the impurity regions comprises,

low concentration impurity regions that are arranged on the second portions below the spacers, and

high concentration impurity regions that are arranged on the second portions between the low concentration impurity regions and have the same conductive type as the low concentration impurity regions.

10. The vertical non-volatile memory device of claim 1, further comprising:

metal silicide layers formed between the impurity regions and the conductive lines.

11. The vertical non-volatile memory device of claim 1, wherein the conductive lines comprises a metal layer selected from among a tungsten (W) layer, an aluminium (Al) layer, and a copper (Cu) layer.

19. An electric-electronic system comprising:

an input/output device via which data is input and output;

an interface receiving and transmitting the data;

a memory chip having the non-volatile memory chip of claim 1, the memory chip storing the data; and

a controller controlling the input/output device, the interface, and the memory chip.

12. A vertical non-volatile memory device comprising:

a semiconductor substrate including a cell region and a peripheral region;

cell string units that are formed on first portions within the cell region and are vertically arranged with respect to a surface of the semiconductor substrate;

impurity regions formed on second portions between the cell string units within the cell region; and

conductive lines formed on the impurity regions,

wherein the bottom surfaces of the gate dielectric layers of the bottommost selecting transistors in the cell string units are located lower than the top surface of the semiconductor substrate in the peripheral region.

13. The vertical non-volatile memory device of claim 12, wherein each of the cell string units comprises selecting transistors and a plurality of memory cell transistors arranged between the selecting transistors, wherein

channel layers are formed to contact the first portions and are vertical to the surface of the semiconductor substrate, and wherein

the selecting transistors and the plurality of memory cell transistors are arranged on the sidewalls of the channel layers.

14. The vertical non-volatile memory device of claim 13, wherein the bottom surfaces of the gate dielectric layers are formed at a position where the channel layers and the semiconductor substrate contact each other.

15. The vertical non-volatile memory device of claim 12, further comprises:

insulation pillars that are formed on the centers of the first portions and vertical to the surface of the semiconductor substrate, wherein

the cell string units comprises,

channel layers that surround the bottom surfaces and the sidewalls of the insulation pillars and contact the first portions of the semiconductor substrate at the bottom surfaces of the gate dielectric layers,

gates of selecting transistors that are arranged on the channel layers formed on two opposite sidewalls of each of the insulation pillars and are vertically stacked with respect to the surface of the semiconductor substrate, and

gates of memory cell transistors that are arranged between the gates of the selecting transistors.

16. The vertical non-volatile memory device of claim 15, further comprising:

gate dielectric layers interposed between the channel layers and the gates,

wherein the gate dielectric layers are formed on the sidewalls of the gates to be vertical to the surface of the substrate or formed to surround the sidewalls, the bottom surfaces, and the top surfaces of the gates.

17. The vertical non-volatile memory device of claim 12, wherein the conductive lines comprise metal silicide layers formed on the impurity regions, wherein

the metal silicide layers are formed at a position lower than the bottom surfaces of the gate dielectric layers.

18. The vertical non-volatile memory device of claim 17, wherein the conductive lines comprise the metal silicide layers and metal layers on the metal silicide layers.

20-41. -41. (canceled)