PIPELINE METHOD AND SYSTEM FOR SWITCHING PACKETS

• US 20110002340A1
• Filed: 06/07/2010
• Published: 01/06/2011
• Est. Priority Date: 05/06/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Aris, Davis, Ian Edward
• Granted Patent: US 8,170,044 B2
• Time in Patent Office: Days
• US Class Current: 370/401
• CPC Class Codes: H04L 49/1546 using pipelined operation

Abstract

A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Claims

1. (canceled)

2. A system comprising:

a backplane;

a first pipeline comprising a first packet processor, a first memory, and a backplane manager, wherein the first packet processor is configured to process a packet received by the system and to store packet data corresponding to the packet in the first memory, and wherein the backplane manager is configured to read the packet data from the first memory, compute an appropriate destination for the packet data, and dispatch the packet data to the backplane;

a second pipeline comprising a transmission accumulator, a second memory, and a second packet processor, wherein the transmission accumulator is configured to receive packet data from the backplane and store the packet data in the second memory, and wherein the second packet processor is configured to read the packet data from the second memory and schedule transmission of the packet from the system; and

a path for forwarding the packet data from the first memory to the transmission accumulator without using the backplane.

3. The system of claim 2 further comprising:

a media access controller (MAC), wherein the MAC is configured to forward the packet received by the system to the first packet processor, and wherein the MAC is configured to receive the packet from the second packet processor and transmit the packet received from the second packet processor from the system.

4. The system of claim 2 further comprising:

a CAM processor;

wherein the first packet processor is configured to extract forwarding information from the packet; and

wherein the CAM processor is configured to perform a lookup using the forwarding information.

5. The system of claim 2 wherein the first packet processor is configured to generate a packet header for forwarding the packet through the system.

6. The system of claim 2 wherein the first memory is a dual-port memory that enables the first processor to store the packet data in the first memory independent of processing performed by the backplane manager.

7. The system of claim 2 wherein at least one of the first packet processor, the backplane manager, the transmission accumulator, and the second packet processor is a field programmable gate array (FPGA).

8. The system of claim 2 wherein at least one of the first packet processor, the second packet processor, and the backplane manager is an application-specific integrated circuit (ASIC).

9. The system of claim 2 wherein the second memory comprises a series of first-in first-out structures for the packet data received via the path.

10. A method comprising:

providing, in a network device, a first pipeline comprising a first packet processor, a first memory, and a backplane manager, wherein the first packet processor is configured to process a packet received by the system and to store packet data corresponding to the packet in the first memory, and wherein the backplane manager is configured to read the packet data from the first memory, compute an appropriate destination for the packet data, and dispatch the packet data to a backplane;

providing, in the network device, a second pipeline comprising a transmission accumulator, a second memory, and a second packet processor, wherein the transmission accumulator is configured to receive packet data from the backplane and store the packet data in the second memory, and wherein the second packet processor is configured to read the packet data from the second memory and schedule transmission of the packet from the system; and

enabling the packet data to be forwarded from the first memory to the transmission accumulator without using the backplane.

11. The method of claim 10 wherein:

forwarding the packet received by a media access controller (MAC) to the first packet processor;

forwarding the packet scheduled for transmission from the second packet processor to the MAC; and

forwarding the packet from the network device using the MAC.

12. The method of claim 10 further comprising:

extracting, by the first packet processor, forwarding information from the packet; and

performing a lookup in a CAM using the forwarding information.

13. The method of claim 10 further comprising:

generating, by the first packet processor, a packet header for forwarding the packet through the network device.

14. The method of claim 10 wherein:

the first memory is a dual-port memory; and

enabling the first processor to store the packet data in the first memory independent of processing performed by the backplane manager.

15. The method of claim 10 wherein at least one of the first packet processor, the backplane manager, the transmission accumulator, and the second packet processor is a field programmable gate array (FPGA).

16. The method of claim 10 wherein at least one of the first packet processor, the second packet processor, and the backplane manager is an application-specific integrated circuit (ASIC).

17. The method of claim 10 further comprising detecting when packet data stored in the first memory is to be forwarded to the transmission accumulator using the path.

18. The method of claim 10 further comprising providing a series of first-in first-out structures in the second memory for the packet data received via the path.

19. A network device comprising:

a media access controller (MAC) configured to receive a packet received by the network device;

a first series of elements configured to forward packet data corresponding to the packet from the media access controller (MAC) to a backplane, the first series of elements comprising a first processor and a first memory, the first processor configured to process the packet and store the corresponding packet data in the first memory;

a second series of elements configured to forward the packet data from the backplane to the MAC; and

a path that enables the packet data to be forwarded from an element in the first series of elements to an element in the second series of elements without using the backplane.

20. The network device of claim 19 wherein the path enables the packet data to be forwarded from the first memory to an element in the second series of elements.

21. The network device of claim 19 wherein the path enables the packet data to be forwarded from the first memory to an element in the second series of elements that is configured to receive the packet data forwarded from the first memory using the path or received packet data from the backplane.

22. The network device of claim 19 further comprising:

a chassis comprising a set of slots; and

a blade inserted into a slot from the set of slots, wherein the blade comprises the MAC, the first series of elements, and the second series of elements.

23. The network device of claim 19 wherein at least one element from the first series of elements is a field programmable gate array (FPGA).

24. The network device of claim 19 wherein at least one element from the first series of elements is an application-specific integrated circuit (ASIC).