SECURITY SYSTEM AND METHOD

• US 20110002462A1
• Filed: 09/14/2010
• Published: 01/06/2011
• Est. Priority Date: 12/09/2003
• Status: Active Grant

• Current Assignee: Dominic Kotab
• Original Assignee: Dominic Kotab
• Inventors: Paley, Daniel Noah, Stewart, Roger Green
• Granted Patent: US 8,249,251 B2
• Time in Patent Office: Days
• US Class Current: 380/46
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 67/02 based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 9/3271 using challenge-response

Abstract

A device for generating a seedless pseudo-random number, according to one embodiment, includes a first register containing a secret code; a second register containing a first random number generated locally and a second random number generated at a remote device; and an exclusive OR (XOR) circuit receiving output from the first and second registers and applying an XOR function to the outputs, a result of the XOR function being fed into the second register in a subsequent cycle.

Claims

1. A device for generating a seedless pseudo-random number, comprising:

a first register containing a secret code;

a second register containing a first random number generated locally and a second random number generated at a remote device; and

an exclusive OR (XOR) circuit receiving output from the first and second registers and applying an XOR function to the outputs, a result of the XOR function being fed into the second register in a subsequent cycle.

2. A device as recited in claim 1, wherein the first register is a shifting register.

3. A device as recited in claim 1, wherein the device is an RFID reader.

4. A device as recited in claim 1, wherein the device is an RFID tag.

5. A device as recited in claim 1, wherein the remote device is an RFID reader.

6. A device as recited in claim 1, wherein the remote device is an RFID tag.

7. A device as recited in claim 1, wherein several cycles are executed prior to output of data to the remote device.

8. A device as recited in claim 1, further comprising a clock generator for controlling shifting of the first register, wherein the first register is clocked differently than the second register.

9. A device as recited in claim 8, wherein the clock register periodically stops the first register.

10. A device as recited in claim 8, wherein the clock generator varies the clock signal to the first register based on output from at least the second register.

11. A device as recited in claim 8, wherein the clock generator varies the clock signal to the first register based on an XOR result of output from the first register and output from the second register.

12. A device as recited in claim 8, wherein the clock generator varies the clock signal to the first register based on an OR result obtained by combining an XOR result of selected bits output from the first register and an XOR result of selected bits output from the second register.

13. A method for generating a seedless pseudo-random number, comprising:

storing a secret code in a first register;

storing a locally-generated random number in a second register;

storing a second random number generated at a remote device in the second register;

receiving output from the first and second registers;

applying an exclusive OR (XOR) function to the output from the first and second registers;

feeding a result of the XOR function into the second register in a subsequent cycle.

14. A method as recited in claim 13, wherein the first register is a shifting register.

15. A method as recited in claim 13, wherein the method is implemented by an RFID reader.

16. A method as recited in claim 13, wherein the method is implemented by an RFID tag.

17. A method as recited in claim 13, wherein several cycles are executed prior to output of data to the remote device.

18. A method as recited in claim 13, further comprising controlling shifting of the first register using a clock signal, wherein the first register is clocked differently than the second register.

19. A method as recited in claim 18, further comprising periodically stopping the first register.

20. A method as recited in claim 18, further comprising varying the clock signal to the first register based on output from at least the second register.

21. A method as recited in claim 18, further comprising varying the clock signal to the first register based on an XOR result of output from the first register and output from the second register.

22. A method as recited in claim 18, further comprising varying the clock signal to the first register based on an OR result obtained by combining an XOR result of selected bits output from the first register and an XOR result of selected bits output from the second register.