METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES

• US 20110003422A1
• Filed: 07/02/2009
• Published: 01/06/2011
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: AMF-Nano Corporation
• Original Assignee: Advanced Microfab, LLC
• Inventors: Katragadda, Rakesh, Chalil, Joseph M., Choksi, Nishit A., Kumar, G. Krishna
• Granted Patent: US 7,989,248 B2
• Time in Patent Office: Days
• US Class Current: 438/51
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Claims

1. A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structure comprising the steps of:

providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers;

applying at least one protective layer overlying the CMOS device area;

forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate;

forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers;

applying at least one filler layer in the at least one opening on the semiconductor substrate;

positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside;

applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip;

forming at least one via opening on the insulating layer covering the chip to access at least one contact area;

applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip;

applying a second insulating layer overlying the metallization layer on the at least one chip;

applying at least one interfacial layer;

applying at least one rigid substrate overlying the interfacial layer;

applying at least one secondary protective layer overlying the rigid substrate.

2. The method of claim 1, wherein the CMOS device area includes pre-fabricated structures selected from:

multi level poly, multi level metal with digital logic circuits, operational amplifiers, inverters, analog and digital circuitry, digital switches, and voltage comparators.

3. The method of claim 1, wherein the protective layer is selected from variable temperature polymers including polyimide and parylene and lithographically patternable materials including photoresist materials.

4. The method of claim 1, wherein the step of forming an opening of the protective layer includes patterning the dielectric and metallization layers on the substrate material to create access to the semiconductor.

5. The method of claim 4, wherein the patterning includes photolithographically defining open areas and then etching.

6. The method of claim 5 wherein the etching is selected from:

wet, dry, isotropic, and anisotropic etching.

7. The method of claim 1, wherein the filler material is selected from:

polyimide, silicone, epoxy or their combination.

8. The method of claim 1, wherein the chip is selected from:

commercial CMOS integrated circuits, electronics or diced chips from another MEMS/NEMS fabrication process.

9. The method of claim 8, wherein the CMOS integrated circuits are selected from:

voltage comparators, diodes, op-amps, power management circuits, resistors, capacitors, and inductors.

10. The method of claim 8, wherein MEMS/NEMS chips include transducers selected from chemical and biological, optical, mechanical, radiation, thermal, capacitive, magnetic and electromagnetic, flow, and micro-fluidic transducers

11. The method of claim 1, wherein the first insulation layer covering the chip and the substrate is selected from oxides, nitrides, glass, quartz, and polymers.

12. The method of claim 1, wherein the metallization layer is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.

13. The method of claim 1, wherein the second insulating layer overlying the metallization layer is selected from oxides, nitrides, glass, quartz, and polymers.

14. The method of claim 1, wherein the interfacial material is selected from metals including gold, and tin, alloys, and epoxy including Benzocyclobuten (BCB) and SU8 photoresist.

15. The method of claim 1, wherein the at least one rigid substrate overlying the interfacial layer is selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic and metal.

16. The method of claim 1, wherein the secondary protective layer overlying the rigid substrate is selected from organic encapsulation including nonelastomeric thermoplastics including parylene, thermosetting polymers including silicones, polymides, and epoxies, metals or their combination.

17. A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:

providing a semiconductor substrate having MEMS/NEMS materials including mechanical structural layers and conductive layers;

applying a first insulating layer overlying the MEMS/NEMS materials;

applying at least one protective layer overlying the MEM/NEMS materials;

forming at least one opening on the protective layer to access the semiconductor substrate;

applying at least one filler layer in the at least one opening on the semiconductor substrate;

positioning at least one chip on the filler layer, the chip including a front face and a bare backside;

applying a second insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip;

forming at least one via opening on the insulating layer covering the chip to access at least one contact area;

applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one contact area on the chip;

applying a third insulating layer overlying the metallization layer on the at least one chip;

performing at least one post micro/nano fabrication etching step forming a released structure;

applying at least one interfacial layer;

applying at least one rigid substrate overlying the interfacial layer;

applying at least one secondary protective layer overlying the rigid substrate.

18. The method of claim 17, wherein the first insulating layer includes materials selected from LPCVD deposited materials including oxides and nitrides, polymers including parylene and polyimide, glass, and quartz.

19. The method of claim 17, wherein the mechanical structural layer is selected from LPCVD deposited materials, polymer, metal, and single crystal silicon.

20. The method of claim 19, wherein the LPCVD deposited materials is selected from oxides, nitrides, and polysilicon.

21. The method of claim 20, wherein conductive layer is selected from materials doped with boron or phosphorous, polysilicon, single crystal silicon, aluminum, copper, titanium, chrome, gold, silver, or their combination.

22. The method of claim 19, wherein the polymer is selected from parylene, polyimide and silicone.

23. The method of claim 19, wherein the metal is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.

24. The method of claim 17 wherein the protective layer is selected from variable temperature polymers including polyimide and parylene and lithographically patternable materials including photoresist materials.

25. The method of claim 17, wherein the step of forming an opening of the protective layer includes patterning the dielectric and metallization layers on the substrate material to create access to the semiconductor.

26. The method of claim 25, wherein the patterning includes photolithographically defining open areas and then etching.

27. The method of claim 26 wherein the etching is selected from:

wet, dry, isotropic, and anisotropic etching.

28. The method of claim 17, wherein the filler material is selected from:

polyimide, silicone, epoxy or their combination.

29. The method of claim 17, wherein the chip is selected from:

commercial CMOS integrated circuits, electronics or diced chips from another MEMS/NEMS fabrication process.

30. The method of claim 29, wherein the CMOS integrated circuits are selected from:

voltage comparators, diodes, op-amps, power management circuits, resistors, capacitors, and inductors.

31. The method of claim 29, wherein MEMS/NEMS chips include transducers selected from chemical and biological, optical, mechanical, radiation, thermal, capacitive, magnetic and electromagnetic, flow, and micro-fluidic transducers

32. The method of claim 17, wherein third insulation layer covering the chip and the substrate comprises materials selected from polymers, oxide, nitride, glass quartz layer covering the chip and the substrate is selected from oxides, nitrides, glass, quartz, and polymers.

33. The method of claim 17, wherein the metallization layer is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.

34. The method of claim 17, wherein the second insulating layer overlying the chip is selected from oxides, nitrides, glass, quartz, and polymers.

35. The method of claim 17, wherein the third insulating layer overlying the metallization layer is selected from oxides, nitrides, glass, quartz, and polymers.

36. The method of claim 35, wherein the polymers are selected from parylene, and polyimide.

37. The method of claim 17, wherein the micro/nano fabrication etching step is selected from wet, dry, isotropic, and anisotropic etching.

38. The method of claim 17, wherein the micro/nano fabrication etching further comprises surface micromachining, bulk micromachining, dry etching, and chemical etching from a backside of the substrate.

39. The method of claim 17, wherein the interfacial material is selected from metals including gold, and tin, alloys, and epoxy including Benzocyclobuten (BCB) and SU8 photoresist.

40. The method of claim 17, wherein the at least one rigid substrate overlying the interfacial layer is selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic and metal.

41. (canceled)