THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE

• US 20110003438A1
• Filed: 09/14/2010
• Published: 01/06/2011
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Sang-Yun Lee
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Granted Patent: US 8,367,524 B2
• Time in Patent Office: Days
• US Class Current: 438/121
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/0101 Neon [Ne]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device.

Claims

1. A method, comprising:

providing an interconnect region; and

coupling a multiple layer semiconductor structure to the interconnect region through bonding.

2. The method of claim 1, further including processing the multiple layer semiconductor structure to form a mesa structure bonded to the interconnect region.

3. The method of claim 2, further including processing the mesa structure to form a vertically oriented semiconductor device.

4. The method of claim 1, wherein the multiple layer semiconductor structure includes single crystalline semiconductor material.

5. The method of claim 1, further including forming the multiple layer semiconductor structure by depositing a blanket layer of semiconductor material on a detach region.

6. The method of claim 1, wherein the multiple layer semiconductor structure is coupled to the interconnect region through a bonding region.

7. The method of claim 6, wherein the interconnect region includes a conductive line in communication with the bonding region.

8. The method of claim 6, further including forming the bonding region by forming a metal layer on the interconnect region.

9. The method of claim 6, wherein the bonding region covers a major surface of the interconnect region.

10. The method of claim 9, wherein the interconnect region includes a conductive line in communication with the bonding region.

11. A method, comprising:

providing an interconnect region carried by an electronic circuit;

providing a substrate which includes a support structure which carries a multiple layer structure; and

coupling the multiple layer structure to the interconnect region through bonding.

12. The method of claim 11, wherein the multiple layer structure is coupled to the interconnect region by establishing a bonding interface.

13. The method of claim 12, wherein the interconnect region includes a conductive line in communication with the bonding region.

14. The method of claim 11, wherein the multiple layer structure includes single crystal semiconductor material.

15. The method of claim 11, further including removing the support structure from the multiple layer structure so the multiple layer structure is carried by the interconnect region.

16. The method of claim 11, further including processing the multiple layer structure to form a mesa structure.

17. The method of claim 11, wherein the substrate includes a detach region between the support structure and multiple layer structure.

18. The method of claim 17, wherein the detach region includes porous silicon.

19. A method, comprising:

coupling a semiconductor structure to an interconnect region through a bonding region;

wherein the interconnect region includes a conductive line in communication with the bonding region.

20. The method of claim 19, wherein the interconnect region includes a plurality of conductive lines in communication with the bonding region.

21. The method of claim 19, further including separating the semiconductor structure from a support substrate so the semiconductor structure is carried by the interconnect region.

22. The method of claim 21, wherein the structure includes a cleaved surface facing away from the bonding region.

23. The method of claim 19, wherein the structure includes a planarized surface facing the bonding region.

24. The method of claim 19, further including forming the bonding region by forming a metal layer on the interconnect region.

25. The method of claim 19, wherein the semiconductor structure includes single crystal semiconductor material.

26. The method of claim 19, wherein the semiconductor structure includes a pn junction.

27. The method of claim 19, wherein the bonding region covers a major surface of the interconnect region.