Method for Enhancing the Memory Bandwidth Available Through a Memory Module

• US 20110004709A1
• Filed: 09/05/2007
• Published: 01/06/2011
• Est. Priority Date: 09/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 8,019,919 B2
• Time in Patent Office: Days
• US Class Current: 710/51
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Claims

1. A method of accessing memory devices of a memory module, comprising:

receiving, in a memory hub device integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module;

selecting one of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the access request; and

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein;

the first memory device data interface communicates with the first set of memory devices,

the second memory device data interface communicates with the second set of memory devices,

the first set of memory devices are separate from the second set of memory devices, and

the first memory device data interface is separate from the second memory device data interface.

2. The method of claim 1, wherein the access request is received from a memory controller of a data processing device via a memory channel, the memory controller being external to the memory module.

3. The method of claim 1, wherein selecting one of the first memory device data interface or the second memory device data interface comprises performing the selection in a memory hub controller integrated in the memory module, and wherein based upon the selection, the memory hub controller sends a control signal to a multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.

4. The method of claim 3, wherein accessing one of the first set of memory devices or the second set of memory devices comprises driving, by the memory hub controller, one or more of the first set of memory devices or the second set of memory devices, using a memory device address and control bus, and asserting one of a read data flow selector signal or a write data flow selector signal to at least one multiplexer integrated in the memory module.

5. The method of claim 3, wherein if the access request is a read access request, selecting one of the first memory device data interface integrated in the memory hub device or the second memory device data interface integrated in the memory hub device, comprises:

driving, by the memory hub controller, a read data flow selector signal to the multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue.

6. The method of claim 3, wherein if the access request is a write access request, selecting one of the first memory device data interface integrated in the memory hub device or the second memory device data interface integrated in the memory hub device, comprises:

driving, by the memory hub controller, a write data flow selector signal to one of a first multiplexer or a second multiplexer, for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, based on address information in the access request.

7. The method of claim 6, wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.

8. The method of claim 3, wherein accessing the one of the first set of memory devices or the second set of memory devices comprises:

accessing both the first set of memory devices, via selection of the first memory device data interface, and the second set of memory devices, via selection of the second memory device data interface, in substantially a parallel manner, under control of the memory hub controller in response to the memory hub controller receiving a first access request and a subsequent second access request.

9. The method of claim 8, wherein the first access request is one of a read access request or a write access request, and wherein the second access request is one of a read access request or a write access request.

10. The method of claim 8, wherein the first access request and the second access request are memory read access requests, and wherein read data from the first memory read access request and the second memory read access request are directly transferred to an external memory controller.

11. The method of claim 8, wherein the first access request and the second access request are memory read access requests, and wherein read data from the first memory read access request and the second memory read access request are queued prior to being transferred to an external memory controller.

12. The method of claim 1, wherein the access request is received by a memory hub controller of the memory hub device via a link interface coupling an external memory controller to the memory hub controller, and wherein the first and second set of memory devices send and receive data to and from the external memory controller via the link interface.

13. The method of claim 12, wherein a first multiplexer is integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, and wherein the first multiplexer is configured to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller.

14. The method of claim 13, wherein the memory hub device further comprises:

a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being configured to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and

a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being configured to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.

15. The method of claim 1, wherein accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface comprises:

processing a first memory access request via the first memory device data interface; and

processing, in parallel, a second memory access request via the second memory device data interface at substantially a same time as the processing of the first memory access request.

16. The method of claim 1, wherein the memory module is part of a data processing device.

17. The method of claim 1, wherein the memory module is part of a main memory of a data processing device.

18. The method of claim 1, wherein the memory module is a dual in-line memory module (DIMM).

19. The method of claim 1, wherein the memory module is a single in-line memory module (SIMM).