METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE

• US 20110004715A1
• Filed: 09/17/2010
• Published: 01/06/2011
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Michael A. Rothman, Vincent J. Zimmer
• Inventors: Zimmer, Vincent J., Rothman, Michael A.
• Granted Patent: US 8,001,308 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 2209/5012 Processor sets
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources

Abstract

A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores.

Claims

1. A method comprising:

sequestering two or more processor cores from a plurality of processor cores of a computing device to form a first group of sequestered processor cores and a second group of non-sequestered processor cores from the plurality of processor cores; and

delivering a management interrupt, accessible only to the first group of sequestered processor cores, for handling.

2. The method of claim 1, wherein the management interrupt is selected from a group of management interrupts comprising a system management interrupt and a platform management interrupt.

3. The method of claim 1, wherein sequestering two or more processor cores comprises selecting the two or more processor cores from a plurality of processor cores of a plurality of processors of the computing device such that at least one processor core of each processor of the plurality of processors is sequestered.

4. The method of claim 1, wherein sequestering two or more processor cores comprises selecting the two or more processor cores of the first group of sequestered processor cores using a virtual synchrony algorithm.

5. The method of claim 1, wherein sequestering two or more processor cores comprises selecting the two or more processor cores of the first group of sequestered processor cores from a sub-set of processor cores of the plurality of processor cores that are designated as hot spare cores.

6. The method of claim 1, further comprising broadcasting the management interrupt from at least one of the processor cores of the first group of sequestered processor cores to one or more processor cores of the second group of non-sequestered processor cores.

7. The method of claim 1, further comprising handling the management interrupt with the one or more processor cores of the first group of sequestered processor cores without disrupting the operating of the processor cores of the second group of non-sequestered processor cores.

8. The method of claim 1, further comprising:

un-sequestering the two or more processor cores forming the first group of sequestered processor cores; and

sequestering two or more processor cores of the plurality of processor cores to form a second group of sequestered processor cores different from the first group of sequestered processor cores.

9. The method of claim 1, further comprising removing a first processor core from the first group of sequestered processing cores in response to the first processor core failing.

10. A non-transitory machine readable medium, comprising a plurality of instructions, that in response to being executed, result in a computing device

sequestering at least one processor core from other processor cores of each processor of a multi-processor computing device such that no processor has every associated processor core sequestered;

and

configuring the computing device to deliver management interrupts accessible only to the sequestered at least one processor core.

11. The medium as recited in claim 10, wherein delivering management interrupts accessible only to the sequestered at least one processor core further comprises not delivering the management interrupts to the other processor cores of each processor of the computing device.

12. The medium as recited in claim 10, wherein the management interrupts are generated in response to an event.

13. The medium of claim 10, wherein

management interrupts are system management interrupts, and

the plurality of instructions further result in the computing device, configuring the computing device to deliver system management interrupts to the at least one sequestered processor core of each processor and to not deliver the system management interrupts to the other processor cores of each processor of the computer device.

14. The medium of claim 10, wherein

management interrupts are platform management interrupts, and

the plurality of instructions further result in the computing device, configuring the computing device to deliver platform management interrupts to the at least one sequestered processor core of each processor and to not deliver the platform management interrupts to the other processor cores of each processor of the computer device.

15. The medium of claim 10, wherein the plurality of instructions further result in the computing device sequestering at least one processor core from other processor cores of each processor of the computing device by using a virtual synchrony algorithm.

16. The medium of claim 10, wherein the plurality of instructions further result in the computing device un-sequestering at least one of the sequestered processor cores.

17. The medium of claim 10, wherein the plurality of instructions further result in the computing device selecting the at least one processor core from other processor cores of each processor of the computing device from a sub-set of processor cores that are designated as hot spare cores.

18. A computing device comprising of:

a plurality of processor cores; and

a memory device coupled to the plurality of processor cores, the memory device having stored therein a plurality of instructions which when executed by at least one of the plurality of cores causes the at least one plurality of cores to;

sequester at least two processor cores from the plurality of processor cores to form a first group of sequestered cores and a second group of non-sequestered processor cores from the plurality of processor cores; and

deliver a management interrupt accessible only to the first group of sequestered processor cores for handling.

19. The computing device as recited in claim 18, wherein delivering management interrupts accessible only to the first group of sequestered cores further comprises not delivering the management interrupts to the second group of non-sequestered processor cores.

20. The computing device of claim 18, wherein the management interrupt is selected from a group of management interrupts comprising a system management interrupt and a platform management interrupt.

21. The computing device of claim 18, wherein to sequester at least two processor cores comprises to select the at least two processor cores from a plurality of processor cores of a plurality of processors of the computing device such that at least one processor core of each processor of the plurality of processors is sequestered.

22. The computing device of claim 18, wherein to sequester at least two processor cores comprises to select the two or more processor cores of the first group of sequestered processor cores using a virtual synchrony algorithm.

23. The computing device of claim 18, wherein the plurality of instructions further cause the at least one processor core to broadcast the management interrupt from at least one of the processor cores of the first group of sequestered processor cores to one or more processor cores of the second group of non-sequestered processor cores.