Node Identification for Distributed Shared Memory System

• US 20110004733A1
• Filed: 04/06/2010
• Published: 01/06/2011
• Est. Priority Date: 04/26/2007
• Status: Abandoned Application

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: 3leaf Networks Incorporated (Dinglong Culture Co., Ltd.)
• Inventors: Krakirian, Shahe Hagop, Akkawi, Isam
• Application Number:
  US12/755,113
• Publication Number:
  US 20110004733A1
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

An example embodiment of the present invention provides processes relating to a connection/communication protocol and a memory-addressing scheme for a distributed shared memory system. In the example embodiment, a logical node identifier comprises bits in the physical memory addresses used by the distributed shared memory system. Processes in the embodiment include logical node identifiers in packets which conform to the protocol and which are stored in a connection control block in local memory. By matching the logical node identifiers in a packet against the logical node identifiers in the connection control block, the processes ensure reliable delivery of packet data. Further, in the example embodiment, the. logical node identifiers are used to create a virtual server consisting of multiple nodes in. the distributed shared memory system.

Claims

1. A method, comprising:

receiving, at a distributed shared memory circuit of a first node in a distributed shared memory system, a message from a second node in the distributed shared memory system comprising a plurality of nodes each having a unique logical unit identifier, wherein the message indicates a memory operation related to a local memory of the first node and identifies a memory address;

if a first plurality of contiguous bits of the memory address equal a logical node identifier of the first node, changing the first plurality of contiguous bits to a predetermined value;

if the first plurality of contiguous bits of the memory address equal the predetermined value, changing the first plurality of contiguous bits to the logical node identifier of the first node;

forwarding the message to a processor of the first node for processing.

2. The method of claim 1 wherein the predetermined value is zero.

3. The method of claim 1 wherein the first set of contiguous bits of the memory address are the most significant bits.

4. The method of claim 1 wherein the plurality of nodes internally access their respective local memories having the first plurality of contiguous bits set to the predetermined value.

5. The method of claim 1 wherein the plurality of nodes access the local memory of the node having a logical unit identifier equal to the predetermined value using its own respective logical node identifier.

6. The method of claim 1 wherein the memory operation is a read command.

7. The method of claim 1 wherein the memory operation is a write command.

8. The method of claim 1 wherein the memory operation is a probe.

9. A method comprising

receiving, at a distributed shared memory circuit of a first node in a distributed shared memory system, a message from a processor of the first node identifying a memory operation related to a local memory of a second node in the distributed shared memory system comprising a plurality of nodes each having a unique logical unit identifier, wherein the message identifies a memory address;

if a first plurality of contiguous bits of the memory address equal a logical node identifier of the first node, changing the first plurality of contiguous bits to a predetermined value;

if the first plurality of contiguous bits of the memory address equal the predetermined value, changing the first plurality of contiguous bits to the logical node identifier of the first node;

forwarding the message to the second node for processing.

10. The method of claim 9 wherein the predetermined value is zero.

11. The method of claim 9 wherein the first set of contiguous bits of the memory address are the most significant bits.

12. The method of claim 9 wherein the plurality of nodes internally access their respective local memories having the first plurality of contiguous bits set to the predetermined value.

13. The method of claim 9 wherein the plurality of nodes access the local memory of the node having a logical unit identifier equal to the predetermined value using its own respective logical node identifier.

14. The method of claim 9 wherein the memory operation is a read command.

15. The method of claim 9 wherein the memory operation is a write command.

16. The method of claim 9 wherein the memory operation is a probe.

17. A distributed shared memory system, comprising:

a plurality of interconnected nodes, wherein each node has a logical node identifier comprising a plurality of contiguous bits;

wherein each of the nodes comprises one or more processors and a local memory; and

wherein each of the nodes further comprises a distributed memory logic circuit operative to share the local memory of a respective node in a distributed shared memory system to create a shared memory in connection with other nodes of the plurality of nodes accessible using binary addresses comprising a plurality of bits, wherein a first set of contiguous bits of the binary addresses of the shared memory correspond to a logical node identifier of a node in the plurality of nodes, and

wherein the one or more processors of each of the nodes are operative to access the local memory of its own node having the first set of contiguous bits of the binary addresses set to a uniform predetermined value; and

wherein the distributed memory logic circuit is further operative to map the uniform predetermined value to the logical node identifier of the local node in memory management traffic transmitted between the nodes that include binary addresses of the shared memory.

18. The system of claim 17 wherein each of the one or more processors access the local memory of the node having a logical node identifier equal to the predetermined value using the logical node identifier of its own node.

19. The method of claim 17 wherein the predetermined value is zero.

20. The method of claim 17 wherein the first set of contiguous bits of the memory address are the most significant bits.

21. The method of claim 17 wherein the distributed memory logic circuit is operative to

if a first plurality of contiguous bits of the binary address equal a logical node identifier of the node, change the first plurality of contiguous bits to the predetermined value;

if the first plurality of contiguous bits of the memory address equal the predetermined value, change the first plurality of contiguous bits to the logical node identifier of the node.