Variable-Cycle, Event-Driven Multi-Execution Flash Processor
First Claim
1. A processing core, comprising:
- an instruction register unit operable to fetch instructions stored in an instruction memory, wherein each of the instructions requires a number of clock cycles to complete;
an instruction decoder unit coupled to the instruction register unit and operable to provide each of the instructions to an execution unit;
a plurality of execution units configured to perform operations associated with accessing non-volatile semiconductor memory units;
at least one of the plurality of execution units operable to execute instructions requiring different numbers of clock cycles to complete; and
the at least one of the plurality of execution units further operable to generate an event control signal in response to the at least one execution unit completing execution of an instruction.
1 Assignment
0 Petitions
Accused Products
Abstract
A Multi-Execution Flash Processor core performs operations associated with accessing non-volatile semiconductor based memory units. Execution units included in the core can execute instructions requiring different numbers of clock cycles to complete by generating an event control signal in response to completing an instruction. The core can be used in a controller to access and control external memory units. Data memory access operations include using an instruction decoder to select one or more execution units to perform an operation associated with the instruction, and generating an event control signal upon completion of the operation. In some cases, executing the instruction includes selecting a second execution unit.
49 Citations
23 Claims
-
1. A processing core, comprising:
-
an instruction register unit operable to fetch instructions stored in an instruction memory, wherein each of the instructions requires a number of clock cycles to complete; an instruction decoder unit coupled to the instruction register unit and operable to provide each of the instructions to an execution unit; a plurality of execution units configured to perform operations associated with accessing non-volatile semiconductor memory units; at least one of the plurality of execution units operable to execute instructions requiring different numbers of clock cycles to complete; and the at least one of the plurality of execution units further operable to generate an event control signal in response to the at least one execution unit completing execution of an instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A solid state drive controller for use with nonvolatile semiconductor based memories, the solid state drive controller comprising:
-
a first processor core; at least one second processor core controlled by the first processor core, configured to respond to memory access commands issued by the first processor core, and configured to control access to at least one nonvolatile semiconductor based memory unit; an interface coupling the second processor core to the at least one nonvolatile semiconductor based memory; the second processor core configured to execute memory access instructions on an event-driven basis, independent of a specific number of clock cycles used by the instructions. - View Dependent Claims (12, 13, 14)
-
-
15. A method comprising:
-
loading into an instruction memory unit a set of instructions configured to perform a memory access operation on a bank of solid state nonvolatile semiconductor based memories; fetching from the instruction memory unit an instruction from the set of instructions; using an instruction decoder unit to select a first execution unit to perform at least one part of an operation associated with the instruction; executing at least a first part of the instruction using the first execution unit, wherein executing the at least a first part of the instruction includes selecting a second execution unit to execute at least a second part of the instruction; and generating an event control signal upon completion of the operation associated with the instruction. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
-
Specification