Method and System of Receiving Data with Enhanced Error Correction

• US 20110004810A1
• Filed: 07/06/2009
• Published: 01/06/2011
• Est. Priority Date: 07/06/2009
• Status: Abandoned Application

• Current Assignee: Himax Media Solutions, Inc. (Himax Technologies Incorporated)
• Original Assignee: Himax Media Solutions, Inc. (Himax Technologies Incorporated)
• Inventors: KAO, SHIANG-LUN, TSAI, TIEN-JU
• Application Number:
  US12/498,345
• Publication Number:
  US 20110004810A1
• Time in Patent Office: Days
• US Class Current: 714/780
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/6577 Representation or format of variables, register sizes or word-lengths and quantization
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end

Abstract

A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s).

Claims

1. A method of receiving data with enhanced error correction, comprising:

generating at least one reliability bit associated with each received data bit; and

correcting at least one error of the data bit according to the associated at least one reliability bit.

2. The method of claim 1, wherein the error is corrected with Hamming code, parity code or cyclic redundancy check (CRC).

3. The method of claim 1, further comprising a step of packing a plurality of the data bits into a data word.

4. The method of claim 3, further comprising a step of detecting or correcting error of the data word before correcting the data bit according to the reliability bit.

5. The method of claim 1, further comprising a step of normalizing the at least one reliability bit such that the reliability bit having greater value possesses stronger reliability than the reliability bit having smaller value.

6. The method of claim 1, wherein the step of correcting the error according to the reliability bit comprises:

sorting plural sets of the reliability bits associated with a plurality of the data bits, wherein the sorting is performed according to values of the sets of reliability bits; and

correcting the data bit or bits associated with the set or sets of reliability bits having smaller values than other sets of the reliability bits.

7. The method of claim 6, further comprising a step of comparing a threshold with the plural sets of the reliability bits, such that only the set or sets having value less than the threshold are under sorting.

8. The method of claim 1, wherein the step of generating the at least one reliability bit comprises:

sampling the received data; and

quantizing the sampled data to generate at least one sampled bit associated with each data bit.

9. The method of claim 8, further comprising a step of integrating the sampled data before the sampled data is quantized.

10. The method of claim 1, wherein the step of generating the at least one reliability bit comprises:

sampling the received data to generate at least one sampled bit associated with each data bit; and

hard-deciding each of the at least one sample bit to be one of two logic states.

11. A system of receiving data with enhanced error correction, comprising:

a soft-decision slicer for generating at least one reliability bit associated with each received data bit; and

an enhanced bit error corrector for correcting at least one error of the data bit according to the associated at least one reliability bit.

12. The system of claim 11, wherein the error is corrected with Hamming code, parity code or cyclic redundancy check (CRC).

13. The system of claim 11, further comprising a serial-to-parallel converter for packing a plurality of the data bits into a data word.

14. The system of claim 13, further comprising an error correction control (ECC) processor for detecting or correcting error of the data word before correcting the data bit according to the reliability bit in the enhanced bit error corrector.

15. The system of claim 11, wherein the soft-decision slicer performs:

normalizing of the at least one reliability bit such that the reliability bit having greater value possesses stronger reliability than the reliability bit having smaller value.

16. The system of claim 11, wherein the enhanced bit error corrector performs the steps of:

sorting plural sets of the reliability bits associated with a plurality of the data bits, wherein the sorting is performed according to values of the sets of reliability bits; and

correcting the data bit or bits associated with the set or sets of reliability bits having smaller values than other sets of the reliability bits.

17. The system of claim 16, further comprising a step of comparing a threshold with the plural sets of the reliability bits, such that only the set or sets having value less than the threshold are under sorting.

18. The system of claim 11, wherein the soft-decision slicer comprises:

a sampling switch for sampling the received data; and

a quantizer for quantizing the sampled data to generate at least one sampled bit associated with each data bit.

19. The system of claim 18, further comprising an integrator for integrating the sampled data before the sampled data is quantized.

20. The system of claim 11, wherein the soft-decision slicer comprises:

a sampling switch for sampling the received data to generate at least one sampled bit associated with each data bit; and

a hard-decision slicer for hard-deciding each of the at least one sample bit to be one of two logic states.