SCHOTTKY DIODE SWITCH AND MEMORY UNITS CONTAINING THE SAME

• US 20110006276A1
• Filed: 07/13/2009
• Published: 01/13/2011
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Kim, Young Pil, Vaithyanathan, Venugopalan, Tian, Wei, Amin, Nurul, Jin, Insik, Setiadi, Dadi
• Granted Patent: US 8,158,964 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66212 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Claims

1. A switching element comprising:

a first semiconductor layer, the first semiconductor layer having a first portion and a second portion;

a second semiconductor layer, the second semiconductor layer having a first portion and a second portion;

an insulating layer disposed between the first semiconductor layer and the second semiconductor layer;

a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction;

a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction,

wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

2. The switching element according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are independently chosen from:

silicon, silicon containing compounds, germanium, germanium containing compounds, aluminium containing compounds, boron containing compounds, gallium containing compounds, indium containing compounds, cadmium containing compounds, zinc containing compounds, lead containing compounds, and tin containing compounds.

3. The switching element according to claim 1, wherein the first semiconductor layer is crystalline silicon and the second portion is doped with phosphorus (P), boron (B), or arsenic (As).

4. The switching element according to claim 1, wherein the second semiconductor layer is crystalline silicon and the first portion is doped with phosphorus (P), boron (B), or arsenic (As).

5. The switching element according to claim 1, wherein the second portion of the first semiconductor layer and the first portion of the second semiconductor layer are heavily doped with phosphorus (P), boron (B), or arsenic (As).

6. The switching element according to claim 5, wherein the first portion of the first semiconductor layer and the second portion of the second semiconductor layer are not heavily doped.

7. The switching element according to claim 1 further comprising a second insulating layer and a substrate layer wherein the second insulating layer is located between the substrate layer and the first semiconductor layer and the second insulating layer is in contact with the first and second metal contacts.

8. A non volatile memory element comprising:

a switching device comprising;

a first semiconductor layer, the first semiconductor layer having a first portion and a second portion;

a second semiconductor layer, the second semiconductor layer having a first portion and a second portion;

an insulating layer disposed between the first semiconductor layer and the second semiconductor layer;

a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction;

a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction,

wherein the second junction and the third junction are ohmic contacts; and

a non volatile memory cell,

wherein the switching device is electrically connected in series with the non volatile memory cell.

9. The non volatile memory element according to claim 8, wherein the first junction and the fourth junction are Schottky contacts.

10. The non volatile memory element according to claim 8, wherein the second portion of the first semiconductor layer and the first portion of the second semiconductor layer are doped with phosphorus (P), boron (B), or arsenic (As).

11. The non volatile memory element according to claim 8, wherein the first portion of the first semiconductor layer and the second portion of the second semiconductor layer are not doped.

12. The non volatile memory element according to claim 8, wherein the first and second semiconductor layers have substantially the same thicknesses.

13. The non volatile memory element according to claim 8 wherein the non volatile memory cell is a spin torque transfer random access memory (STRAM) stack.

14. A method of forming a switching element comprising the steps of:

providing a layered article, the layered article comprising a first semiconductor layer, an insulating layer, and a second semiconductor layer;

forming a first mask region, wherein the first mask region protects only a first portion of the layered article;

doping only a first portion of the second semiconductor layer using a first energy level;

forming a second mask region, wherein the second mask region protects only a second portion of the layered article, wherein the first portion and the second portion of the layered article only partially overlap;

doping only a second portion of the first semiconductor layer using a second energy level, wherein the first energy level and the second energy level are different, thereby forming a doped layered article;

forming a contact mask on only a portion of the doped layered article;

etching a portion of at least the second semiconductor layer, the insulating layer, and the first semiconductor layer;

forming a first and a second metal contact in the etched regions of the second semiconductor layer, the insulating layer, and the first semiconductor layer.

15. The method according to claim 14, wherein the first energy is less than the second energy.

16. The method according to claim 14, wherein providing the layered article comprises:

providing a first layered structure, the first layered structure comprising a first substrate, a second insulating layer and the first semiconductor layer, wherein the second insulating layer is positioned between the first substrate and the first semiconductor layer;

providing a second layered structure, the second layered structure comprising the insulating layer and the second semiconductor layer;

placing the second layered structure in contact with the first layered structure so that the insulating layer of the second layered structure is adjacent the first semiconductor layer of the first layered structure and bonding the first layered structure to the second layered structure to form the layered article.

17. The method according to claim 16, wherein the second layered structure is formed at least in part by oxidizing a silicon wafer.

18. The method according to claim 16, wherein the second layered structure is formed at least in part by depositing an insulating material on a silicon.

19. The method according to claim 14, wherein the first and second mask regions are configured to leave a portion of the layered article undoped.

20. The method according to claim 18, wherein the undoped portion of the layered article is substantially coincident with the portion of the doped layered article that is masked by the contact mask.