SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME

• US 20110006301A1
• Filed: 07/08/2010
• Published: 01/13/2011
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: HOSOBA, Miyuki, YAMAZAKI, Shunpei, SASAKI, Toshinari, SAKATA, Junichiro, OHARA, Hiroki
• Granted Patent: US 8,294,147 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a connection layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an insulating film covering the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the connection layer; and

a first gate wiring, a second gate wiring, and a source wiring over the insulating film,

wherein the source wiring is electrically connected to the source electrode layer,

wherein the first gate wiring is electrically connected to the gate electrode layer,

wherein the first gate wiring is electrically connected to the second gate wiring through the connection layer, and

wherein the connection layer overlaps the source wiring.

2. The semiconductor device according to claim 1, wherein each of the source wiring, the first gate wiring, and the second gate wiring includes a conductive material which has lower resistivity than the source electrode layer and the drain electrode layer.

3. The semiconductor device according to claim 1, wherein the source wiring, the first gate wiring, and the second gate wiring include at least one of aluminum and copper.

4. The semiconductor device according to claim 1, wherein the source electrode layer, the drain electrode layer, and the connection layer are formed from the same layer.

5. The semiconductor device according to claim 1, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

6. The semiconductor device according to claim 1, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

7. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a connection layer over the substrate having the insulating surface;

a gate insulating layer over the gate electrode layer and the connection layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an insulating film covering the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a first gate wiring, a second gate wiring, and a source wiring over the insulating film,

wherein the source wiring is electrically connected to the source electrode layer,

wherein the first gate wiring is electrically connected to the gate electrode layer,

wherein the first gate wiring is electrically connected to the second gate wiring through the connection layer, and

wherein the connection layer overlaps the source wiring.

8. The semiconductor device according to claim 7, wherein each of the source wiring, the first gate wiring, and the second gate wiring includes a conductive material which has lower resistivity than the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 7, wherein the source wiring, the first gate wiring, and the second gate wiring include at least one of aluminum and copper.

10. The semiconductor device according to claim 7, wherein the gate electrode layer and the connection layer are formed from the same layer.

11. The semiconductor device according to claim 7, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

12. The semiconductor device according to claim 7, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

13. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a connection layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an insulating film covering the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the connection layer; and

a gate wiring, a first source wiring, and a second source wiring over the insulating film,

wherein the first source wiring is electrically connected to the source electrode layer,

wherein the gate wiring is electrically connected to the gate electrode layer,

wherein the first source wiring is electrically connected to the second source wiring through the connection layer, and

wherein the connection layer overlaps the gate wiring.

14. The semiconductor device according to claim 13, wherein the gate wiring, the first source wiring, and the second source wiring include a conductive material which has lower resistivity than the source electrode layer and the drain electrode layer.

15. The semiconductor device according to claim 13, wherein the gate wiring, the first source wiring, and the second source wiring include at least one of aluminum and copper.

16. The semiconductor device according to claim 13, wherein the source electrode layer, the drain electrode layer, and the connection layer are formed from the same layer.

17. The semiconductor device according to claim 13, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

18. The semiconductor device according to claim 13, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

19. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a connection layer over the substrate having the insulating surface;

a gate insulating layer over the gate electrode layer and the connection layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an insulating film covering the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a gate wiring, a first source wiring, and a second source wiring over the insulating film,

wherein the first source wiring is electrically connected to the source electrode layer,

wherein the gate wiring is electrically connected to the gate electrode layer,

wherein the first source wiring is electrically connected to the second source wiring through the connection layer, and

wherein the connection layer overlaps the gate wiring.

20. The semiconductor device according to claim 19, wherein the gate wiring, the first source wiring, and the second source wiring include a conductive material which has lower resistivity than the source electrode layer and the drain electrode layer.

21. The semiconductor device according to claim 19, wherein the gate wiring, the first source wiring, and the second source wiring include at least one of aluminum and copper.

22. The semiconductor device according to claim 19, wherein the gate electrode layer and the connection layer are formed from the same layer.

23. The semiconductor device according to claim 19, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

24. The semiconductor device according to claim 19, wherein the gate electrode layer, the connection layer, the source electrode layer, and the drain electrode layer are formed using a stacked layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component.

25. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer including a first heat resistant conductive material over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a connection layer, a source electrode layer, and a drain electrode layer each including a second heat resistant conductive material over the gate insulating layer;

forming, over the gate insulating layer, the oxide semiconductor layer, the connection layer, the source electrode layer, and the drain electrode layer, an insulating film which is in contact with part of the oxide semiconductor layer; and

performing dehydration or dehydrogenation on the oxide semiconductor layer after forming the insulating film.

26. The method for manufacturing a semiconductor device, according to claim 25, wherein the dehydration or dehydrogenation is heating under a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or reduced pressure.

27. The method for manufacturing a semiconductor device, according to claim 26, wherein the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

28. The method for manufacturing a semiconductor device, according to claim 26, wherein slow cooling is performed after the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

29. The method for manufacturing a semiconductor device, according to claim 25, wherein an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component is used as the first heat resistant conductive material.

30. The method for manufacturing a semiconductor device, according to claim 25, wherein the first heat resistant conductive material and the second heat resistant conductive material are formed from the same material.

31. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer including a first heat resistant conductive material over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a connection layer, a source electrode layer, and a drain electrode layer each including a second heat resistant conductive material over the gate insulating layer;

forming, over the gate insulating layer, the oxide semiconductor layer, the connection layer, the source electrode layer, and the drain electrode layer, an insulating film which is in contact with part of the oxide semiconductor layer;

performing dehydration or dehydrogenation on the oxide semiconductor layer after forming the insulating film;

removing part of the insulating film and forming a first contact hole which reaches the source electrode layer, and a third contact hole and a fourth contact hole which reach both end portions of the connection layer;

removing part of the insulating film and part of the gate insulating layer, and forming a second contact hole which reaches the gate electrode layer; and

forming, over the insulating film, a source wiring which is connected to the source electrode layer through the first contact hole, a first gate wiring which is connected to the gate electrode layer through the second contact hole and to the connection layer through the third contact hole, and a second gate wiring which is connected to the connection layer through the fourth contact hole.

32. The method for manufacturing a semiconductor device, according to claim 31, wherein the dehydration or dehydrogenation is heating under a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or reduced pressure.

33. The method for manufacturing a semiconductor device, according to claim 32, wherein the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

34. The method for manufacturing a semiconductor device, according to claim 32, wherein slow cooling is performed after the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

35. The method for manufacturing a semiconductor device, according to claim 31, wherein an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component is used as the first heat resistant conductive material.

36. The method for manufacturing a semiconductor device, according to claim 31, wherein the first heat resistant conductive material and the second heat resistant conductive material are formed from the same material.

37. The method for manufacturing a semiconductor device, according to claim 31,

wherein the source wiring, the first gate wiring, and the second gate wiring include a conductive material, and

wherein the conductive material has lower resistivity than the source electrode layer and the drain electrode layer.

38. The method for manufacturing a semiconductor device, according to claim 37, wherein the conductive material includes at least one of aluminum and copper.

39. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer including a first heat resistant conductive material over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

forming a connection layer, a source electrode layer, and a drain electrode layer each including a second heat resistant conductive material over the oxide semiconductor layer;

forming, over the gate insulating layer, the oxide semiconductor layer, the connection layer, the source electrode layer, and the drain electrode layer, an oxide insulating film which is in contact with part of the oxide semiconductor layer;

performing dehydration or dehydrogenation on the oxide semiconductor layer after the oxide insulating film is formed;

removing part of the oxide insulating film and forming a first contact hole which reaches the source electrode layer, and a third contact hole and a fourth contact hole which reach both end portions of the connection layer;

removing part of the oxide insulating film and part of the gate insulating layer, and forming a second contact hole which reaches the gate electrode layer; and

forming, over the oxide insulating film, a first source wiring which is connected to the source electrode layer through the first contact hole and to the connection layer through the third contact hole, a second source wiring which is connected to the connection layer through the fourth contact hole, and a gate wiring which is connected to the gate electrode layer through the second contact hole.

40. The method for manufacturing a semiconductor device, according to claim 39, wherein the dehydration or dehydrogenation is heating under a nitrogen atmosphere, an oxygen atmosphere, a rare gas atmosphere, or reduced pressure.

41. The method for manufacturing a semiconductor device, according to claim 40, wherein the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

42. The method for manufacturing a semiconductor device, according to claim 40, wherein slow cooling is performed after the dehydration or dehydrogenation is heating at a temperature of higher than or equal to 350°

C. and lower than a strain point of the substrate.

43. The method for manufacturing a semiconductor device, according to claim 39, wherein an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium;

an alloy including any of these elements as a component;

or a nitride including any of these elements as a component is used as the first heat resistant conductive material.

44. The method for manufacturing a semiconductor device, according to claim 39, wherein the first heat resistant conductive material and the second heat resistant conductive material are formed from the same material.

45. The method for manufacturing a semiconductor device, according to claim 39,

wherein the first source wiring, the second source wiring, and the gate wiring include a conductive material, and

wherein the conductive material has lower resistivity than the source electrode layer and the drain electrode layer.

46. The method for manufacturing a semiconductor device, according to claim 45, wherein the conductive material includes at least one of aluminum and copper.