Novel Structure for Flash Memory Cells

• US 20110006355A1
• Filed: 04/22/2010
• Published: 01/13/2011
• Est. Priority Date: 07/08/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Shih-Chang, Tsai, Chia-Shiung, Tsao, Tsun Kai, Shen, Ming-Hui, Lo, Chi-Hsin
• Granted Patent: US 8,445,953 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a floating gate overlying the semiconductor substrate;

a word-line adjacent to the floating gate;

an erase gate adjacent to a side of the floating gate opposite the word-line;

a first sidewall disposed between the floating gate and the word-line, the first sidewall having a first characteristic; and

a second sidewall disposed between the floating gate and the erase gate, the second sidewall having a second characteristic;

wherein the first characteristic is different from the second characteristic.

2. The semiconductor structure of claim 1, further comprising:

a control gate disposed on the floating gate;

a separation layer disposed between the control gate and the floating gate; and

wherein the first sidewall extends up a side of the control gate.

3. The semiconductor structure of claim 1, wherein the first sidewall comprises:

a first oxide layer disposed between the floating gate and the word-line; and

an isolation layer disposed between the word-line and the first oxide layer.

4. The semiconductor structure of claim 1, wherein the second sidewall comprises a second oxide layer disposed between the floating gate and the erase gate.

5. The semiconductor structure of claim 1, wherein the first sidewall is formed from materials different from materials used to form the second sidewall.

6. The semiconductor structure of claim 1, wherein the first sidewall is thicker than the second sidewall.

7. The semiconductor structure of claim 1, further comprising:

a second floating gate disposed on the semiconductor substrate, the second floating gate disposed on a side of the erase gate opposite the floating gate;

a second word-line disposed on the semiconductor substrate and adjacent to a side of the second floating gate opposite the erase gate; and

a third sidewall disposed between the second floating gate and the second word-line.

8. The semiconductor structure of claim 7, further comprising a fourth sidewall disposed between the second floating gate and the erase gate.

9. The semiconductor structure of claim 8, wherein the fourth sidewall is thinner than the third sidewall.

10. A semiconductor structure comprising:

a semiconductor substrate;

a first floating gate disposed on the semiconductor substrate;

a first word-line adjacent to the first floating gate;

an erase gate adjacent to a side of the first floating gate opposite the first word-line;

a first control gate disposed on the first floating gate;

a first separation layer disposed between the first control gate and the first floating gate;

a first oxide layer disposed between the first floating gate and the first word-line;

a first isolation layer disposed between the first word-line and the first oxide layer; and

a second oxide layer disposed between the first floating gate and the erase gate.

11. The semiconductor structure of claim 10, wherein the first oxide layer and the first isolation layer extend up a side of the first control gate.

12. The semiconductor structure of claim 10, further comprising:

a second floating gate adjacent to the erase gate on a side of the erase gate opposite the first floating gate;

a second word-line adjacent to the second floating gate on a side of the second floating gate opposite the erase gate;

a third oxide layer disposed between the second floating gate and the second word-line;

a second isolation layer disposed between the second word-line and the third oxide layer; and

a fourth oxide layer disposed between the first floating gate and the erase gate.

13. The semiconductor structure of claim 12, further comprising, a common source region disposed in the semiconductor substrate and in between the first floating gate and the second floating gate.

14. The semiconductor structure of claim 12, wherein the second oxide layer and the fourth oxide layer are substantially equal in thickness.

15. The semiconductor structure of claim 12, wherein the first oxide layer and the third oxide layer are substantially equal in thickness.

16. The semiconductor structure of claim 12, wherein the first isolation layer and the second isolation layer are formed from the same material.

17. The semiconductor structure of claim 16, wherein the first isolation layer and the second isolation layer are substantially equal in thickness.

18. The semiconductor structure of claim 10, wherein the first isolation layer is about 70 Å

thick.

19. The semiconductor structure of claim 18, wherein the isolation layer comprises a nitride layer.

20. The semiconductor structure of claim 10, wherein the first oxide layer is about 150 Å

thick.