METHOD OF FORMING A HIGH-K GATE DIELECTRIC LAYER

• US 20110006375A1
• Filed: 09/21/2010
• Published: 01/13/2011
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ramin, Manfred, Alshareef, Husam, Pas, Michael F.
• Granted Patent: US 8,304,333 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02156 the material containing at least one rare earth element, e.g. silicate of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a dielectric layer, including;

forming a silicon oxide layer on a semiconductor substrate;

nitriding the silicon oxide layer to form a nitrided silicon oxide layer; and

incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer;

wherein incorporating the lanthanide atoms includes forming a lanthanide metal layer on the nitrided silicon oxide layer, and then annealing the lanthanide metal layer and the nitrided silicon oxide layer.

2. The method of claim 1, wherein forming the lanthanide metal layer includes depositing lanthanide metal at a deposition rate of about 0.5 nm per second.

3. The method of claim 1, wherein the anneal includes thermally annealing in an atmosphere having about 5 or more percent oxygen.

4. The method of claim 1, wherein the anneal is a thermal anneal also configured as a spike anneal that activates and diffuses implanted source and drain dopants.

5. A method for manufacturing a semiconductor device, comprising:

forming a gate electrode over a gate dielectric, including;

forming a silicon oxide layer on a semiconductor substrate;

nitriding the silicon oxide layer to form a nitrided silicon oxide layer;

forming a lanthanide metal layer on the nitrided silicon oxide layer;

forming a gate electrode layer over the nitrided silicon oxide layer; and

annealing the lanthanide metal layer and the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.

6. The method of claim 5, wherein annealing the lanthanide metal layer and the nitrided silicon oxide layer comprises a thermal anneal performed prior to forming the gate electrode layer.

7. The method of claim 5, wherein annealing the lanthanide metal layer and the nitrided silicon oxide layer comprises a thermal anneal performed after forming the gate electrode layer.

8. The method of claim 5, wherein forming the gate electrode layer comprises forming a non-lanthanide metal layer over the gate dielectric layer;

forming a barrier layer over the non-lanthanide metal layer; and

forming a polysilicon layer over the barrier layer.

9. The method of claim 5, wherein annealing the lanthanide metal layer and the nitrided silicon oxide layer comprises performing a thermal anneal in an atmosphere having about 5 percent or higher oxygen.

10. The method of claim 5, further comprising implanting hafnium atoms into the nitrided silicon oxide layer.

11. The method of claim 10, wherein implanting the hafnium atoms includes implanting hafnium with a dosage of 5E14 to 5E15 atom/cm² at an implantation energy of about 20 to 40 keV.

12. A semiconductor device, comprising:

one or more nMOS transistors on or in a semiconductor substrate, including;

a gate dielectric layer on the substrate, the gate dielectric layer consisting essentially of a lanthanide silicon oxynitride layer;

a gate electrode on the gate dielectric layer;

source and drain structures adjacent to the gate dielectric layer;

one or more pMOS transistors on or in the substrate, including;

a second gate dielectric layer on the substrate, the second gate dielectric layer being substantially lanthanide-free;

a second gate electrode on the lanthanide-free gate dielectric layer;

second source and drain structures adjacent to the lanthanide-free gate;

insulating layers over the nMOS transistors and pMOS transistors; and

interconnects in the insulating layers, wherein the interconnects electrically couple the nMOS and the pMOS transistors.

13. The device of claim 12, wherein the gate electrodes and the second gate electrode are configured to have different work functions from each other.

14. The device of claim 12, wherein the nMOS and pMOS transistors are configured to form a SRAM device.

15. The device of claim 12, wherein lanthanide atoms are implanted into a nitrided silicon oxide layer of the nMOS transistor to form the lanthanide silicon oxynitride layer while the pMOS transistors are masked.