NICKEL-TITANUM CONTACT LAYERS IN SEMICONDUCTOR DEVICES

• US 20110006409A1
• Filed: 07/13/2009
• Published: 01/13/2011
• Est. Priority Date: 07/13/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kim, Suku, Pierce, Jim, Murphy, James J., Beggs, William S., Purtell, Robert J., Gruenhagen, Michael D.
• Application Number:
  US12/501,849
• Publication Number:
  US 20110006409A1
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/4827 Materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described.

Claims

1. A semiconductor device, comprising:

a silicon substrate containing an integrated circuit with a drain on a backside of the substrate;

a contact layer containing TiNi contacting the drain on the backside, the contact layer comprising a nickel silicide at the interface with the silicon substrate;

a soldering layer on the contact layer;

an oxidation reducing layer on the soldering layer;

a solder bump on the oxidation prevention layer; and

a lead frame attached to the solder bump.

2. The device of claim 1, wherein the TiNi contact layer contains about 0.5 to about 95.5 wt % Ni.

3. The device of claim 1, wherein the TiNi contact layer contains about 50 to about 55.6 wt % Ni.

4. The device of claim 1, wherein the TiNi contact layer contains about 51 wt % Ni.

5. The device of claim 1, wherein the thickness of the contact layer can range from about 0.1 to about 10 μ

m.

6. The device of claim 1, wherein the thickness of the nickel silicide layer can range from about 0.1 to about 8 μ

m.

7. The device of claim 1, wherein the soldering layer comprises Ni, Ni₉₃V₇, Cu, Ni doped Si, or combinations thereof.

8. The device of claim 1, wherein the oxidation reducing layer comprises Ag, Au, Cu, Pd, Pt, or combinations thereof.

9. The device of claim 1, wherein the ratio of Ti to Ni in the contact layer can be adjusted to change the metal-induced wafer warpage of the substrate.

10. A DMOS semiconductor device, comprising:

a silicon substrate containing an integrated circuit with a drain on a backside of the substrate;

a nickel silicide layer on the backside, the thickness of the nickel silicide layer ranging from about 0.01 to about 8 μ

m;

a contact layer containing TiNi on the nickel silicide, the TiNi containing about 0.5 to about 95.5 wt % Ni and a thickness of about 0.01 to about 10 μ

m;

a soldering layer on the contact layer;

an oxidation reducing layer on the soldering layer;

a solder bump on the oxidation prevention layer; and

a lead frame attached to the solder bump.

11. The device of claim 10, wherein the thickness of the TiNi contact layer can range from about 0.1 to about 3 μ

m.

12. The device of claim 10, wherein the TiNi contact layer contains about 50 to about 55.6 wt % Ni.

13. The device of claim 10, wherein the TiNi contact layer contains about 51 wt % Ni.

14. The device of claim 10, wherein the soldering layer comprises Ni, Ni₉₃V₇, Cu, Si doped Ni, or combinations thereof.

15. The device of claim 10, wherein the oxidation reducing layer comprises Ag, Au, Cu, Pd, or combinations thereof.

16. The device of claim 10, wherein the ratio of Ti to Ni in the contact layer can be adjusted to change the metal-induced wafer warpage of the substrate.

17. The device of claim 10, wherein the thickness of the contact layer can range from about 0.1 to about 3 μ

m.

18. An electronic apparatus containing a semiconductor device, comprising:

a silicon substrate containing an integrated circuit with a drain on backside of the substrate;

a nickel silicide layer on the backside, the thickness of the nickel silicide layer ranging from about 0.01 to about 8 μ

m;

a contact layer containing TiNi on the nickel silicide, the TiNi containing about 0.5 to about 95.5 wt % Ni and a thickness of about 0.01 to about 10 μ

m;

a soldering layer on the contact layer;

an oxidation reducing layer on the soldering layer;

a solder bump on the oxidation prevention layer;

a lead frame attached to the solder bump, the lead frame further connected to a printed circuit board.

19. The apparatus of claim 18, wherein the TiNi contact layer contains about 50 to about 55.6 wt % Ni.

20. The apparatus of claim 18, wherein the TiNi contact layer contains about 51 wt % Ni.

21. The apparatus of claim 18, wherein the ratio of Ti to Ni in the contact layer can be adjusted to change the metal-induced wafer warpage of the substrate.

22. A contact layer for a silicon substrate containing an integrated circuit with a drain on a backside of the substrate, the contact layer comprising:

a nickel silicide layer at the interface with the backside of the silicon substrate, the thickness of the nickel silicide layer ranging from about 0.01 to about 8 μ

m; and

a TiNi layer on the nickel silicide, the TiNi layer containing about 0.5 to about 95.5 wt % Ni and a thickness of about 0.01 to about 10 μ

m.

23. The layer of claim 23, wherein the TiNi layer contains about 50 to about 55.6 wt % Ni.

24. The layer of claim 23, wherein the TiNi layer contains about 51 wt % Ni.

25. The layer of claim 23, wherein the thickness can range from about 0.1 to about 3 μ

m.