Liner Formation in 3DIC Structures

• US 20110006428A1
• Filed: 11/13/2009
• Published: 01/13/2011
• Est. Priority Date: 07/08/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Bao, Tien-I, Chen, Hai-Ching, Tu, Hung-Jung, Lo, Ching-Yu, Chiou, Wen-Chih, Yu, Chen-Hua
• Granted Patent: US 8,264,066 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate comprising a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and

a dielectric liner in the TSV opening, wherein the dielectric liner comprises a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening, and wherein the bottom portion of the dielectric liner has a height greater than a thickness of the sidewall portion of the dielectric liner.

2. The integrated circuit structure of claim 1, wherein a ratio of the height of the bottom portion to the thickness of the sidewall portion is greater than about 2.

3. The integrated circuit structure of claim 1, wherein a top surface of the bottom portion of the dielectric liner is rounded, with a radius greater than about 20 percent of a bottom width of the TSV opening.

4. The integrated circuit structure of claim 3, wherein the radius is greater than about 30 percent of the bottom width of the TSV opening.

5. The integrated circuit structure of claim 1, wherein the dielectric liner has a k value smaller than about 3.5.

6. The integrated circuit structure of claim 1 further comprising a barrier layer on the dielectric liner, and a conductive material on the barrier layer.

7. The integrated circuit structure of claim 6, wherein the conductive material comprises copper.

8. An integrated circuit structure comprising:

a substrate comprising an opening extending into the substrate, wherein the opening has an aspect ratio greater than about 7; and

a dielectric liner in the opening, wherein the dielectric liner comprises a sidewall portion on a sidewall of the opening and a bottom portion on a bottom of the opening, and wherein all thicknesses of the sidewall portion are no greater than a height of the bottom portion.

9. The integrated circuit structure of claim 8, wherein the thicknesses of the sidewall portion increase continuously from upper portions to lower portions.

10. The integrated circuit structure of claim 8, wherein the substrate comprises a silicon substrate, wherein the integrated circuit structure further comprises an inter-layer dielectric (ILD) over the silicon substrate, and wherein the opening extends to a top surface of the ILD.

11. The integrated circuit structure of claim 8, wherein a ratio of the height of the bottom portion to a thickness of the sidewall portion is greater than about 2.

12. The integrated circuit structure of claim 8, wherein the dielectric liner has a k value smaller than about 3.5.

13. The integrated circuit structure of claim 8 further comprising a barrier layer on the dielectric liner, and a conductive material on the barrier layer.

14. The integrated circuit structure of claim 13, wherein the conductive material comprises copper.