METHOD AND APPARATUS FOR INTERROGATING ELECTRONIC EQUIPMENT COMPONENTS

• US 20110006794A1
• Filed: 02/26/2009
• Published: 01/13/2011
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Scanimetrics, Inc.
• Original Assignee: Scanimetrics, Inc.
• Inventors: Slupsky, Steven, Sellathamby, Christopher V., Moore, Brian
• Granted Patent: US 8,829,934 B2
• Time in Patent Office: Days
• US Class Current: 324/754.03
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/308 using non-ionising electromagnetic radiation, e.g. optical radiation investigating or analysing materials by the use of optical means G01N21/00; image analysis G06T7/00
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G08C 17/02 using a radio link
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H04Q 2209/40 using a wireless architecture
• CPC Class Codes: H04Q 2209/75 by polling or interrogating the sub-stations
• CPC Class Codes: H04Q 9/02 Automatically-operated arrangements

Abstract

An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

Claims

1. An apparatus for interrogating an electronic circuit supported by a substrate, comprising:

a tester external to the substrate and comprising a tester transceiver;

a testing circuit supported by the substrate and connected to the electronic circuit, the testing circuit comprising a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester; and

the processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

2. The apparatus of claim 1, wherein the tester comprises a probe and a probe interface, and the tester transceiver is a wireless probe transceiver.

3. The apparatus of claim 2, wherein at least one of the testing circuit and the processor comprises a source measurement unit or a parametric measurement unit.

4. The apparatus of claim 1, wherein the tester comprises a power transmitter and the testing circuit comprises a power receiver.

5. The apparatus of claim 1, wherein the electronic circuit comprises more than one device to be interrogated.

7. The apparatus of claim 1, wherein the substrate is a wafer and the electronic circuit is an integrated circuit in the wafer.

8. The apparatus of claim 1, wherein the electronic circuit is mounted on the substrate.

9. The apparatus of claim 1, wherein the testing circuit comprises power control circuit elements.

12. The apparatus of claim 1, wherein the processor comprises reference circuit element for referencing results of the interrogation.

13. The apparatus of claim 1, wherein the processor comprises at least one signal converter element selected from a group of signal converter consisting of an alternating current/direct current converter, an analog/digital converted, a voltage/frequency converter, a current/frequency converter, a voltage/time converter, and a current/time converter.

17. The apparatus of claim 1, wherein the interrogation corresponding to the instructions comprises a test selected from a group consisting of:

front end tests, back end tests, current-voltage and capacitance-voltage relationships tests, light contamination tests, minority carrier diffusion length test, lifetime and quantitative metallization and diffusion measurement tests, gate oxide integrity (GOI) tests, dielectric parameter tests using on-wafer charge pumps and control dielectric leakage measurements, non-contact capacitance-voltage tests for dielectric charge and interface measurements, capacitance and oxide thickness tests for dielectrics with a charge pump within tunneling range, non-contact capacitance-voltage tests for dielectric charge and interface measurements for dielectrics in the low leakage F-N tunneling, CMP damage monitoring tests, etch damage monitoring tests, plasma damage monitoring tests, surface level effects tests including charge injection, ultra low power tests during the fabrication of semiconductor wafers, and tests for in line process monitoring carried out at various stages of semiconductor wafer fabrication.

19. The apparatus of claim 1, wherein the testing circuit comprises a memory device for storing at least one of testing instructions, testing results and component identification.

6. (canceled)

10-11. -11. (canceled)

14-16. -16. (canceled)

18. (canceled)

20. A method of interrogating an electronic circuit during manufacture of the electronic circuit on a substrate, comprising the steps of:

providing a testing circuit supported by the substrate and connected to the electronic circuit, the testing circuit comprising a processor and a testing circuit transceiver;

transmitting instructions from a tester to the testing circuit;

processing the instructions using the processor; and

interrogating the electronic circuit using an interrogation corresponding to the instructions.

22. The method of claim 20, wherein transmitting instructions from the tester comprises transmitting instructions using a probe interface, a probe and a wireless probe transceiver.

23. The method of claim 20 wherein at least one of the testing circuit and the processor comprises a source measurement unit or a parametric measurement unit.

24. The method of claim 20, further comprising the step of transmitting power to the testing circuit.

26. The method of claim 20, wherein the substrate is a wafer and the electronic circuit is an integrated circuit in the wafer.

27. The method of claim 20, wherein the electronic circuit is mounted on the substrate.

28. The method of claim 20, wherein the testing circuit comprises power control circuit elements.

30. The method of claim 20, further comprising the step of referencing results of the interrogation using an optical reference circuit element.

31. The method of claim 20, wherein the processor performs at least once signal conversion selected from a group consisting of alternating current/direct conversion, analog/digital conversion, voltage/frequency conversion, current/frequency conversion, voltage/time conversion, and current/time conversion.

35. The method of claim 20, wherein interrogating the electronic circuit comprises applying at least one test selected from a group consisting of:

front end tests, back end tests, current-voltage and capacitance-voltage relationships tests, light contamination tests, minority carrier diffusion length test, lifetime and quantitative metallization and diffusion measurement tests, gate oxide integrity (GOI) tests, dielectric parameter tests using on-wafer charge pumps and control dielectric leakage measurements, non-contact capacitance-voltage tests for dielectric charge and interface measurements, capacitance and oxide thickness tests for dielectrics with a charge pump within tunneling range, non-contact capacitance-voltage tests for dielectric charge and interface measurements for dielectrics in the low leakage F-N tunneling, CMP damage monitoring tests, etch damage monitoring tests, plasma damage monitoring tests, surface level effects tests including charge injection; and

ultra low power tests during the fabrication of semiconductor wafers, ultra low power tests to interrogate integrated circuitry in the substrate, and tests for in line process monitoring carried out at various stages of semiconductor wafer fabrication.

37. The method of claim 20, wherein the electronic circuit is interrogated at multiple stages of fabrication.

38. The method of claim 37, further comprising the step of monitoring the multiple stages of fabrication by comparing the results of the interrogations at each stage.

39. The method of claim 20, wherein the testing circuit further comprises a memory device for storing at least one of testing instructions and testing results.

21. (canceled)

25. (canceled)

29. (canceled)

32-34. -34. (canceled)

36. (canceled)

40. A method of interrogating an electronic circuit supported by a substrate during manufacture of the electronic circuit, comprising the steps of:

providing a testing circuit supported by the substrate, the testing circuit comprising a testing circuit transceiver for communicating with a test probe and a processor for processing instructions from the test probe, the testing circuit being electrically connected to the electronic circuit;

instructing the testing circuit to interrogate the electronic circuit using a first interrogation;

applying a manufacturing step to the electronic circuit; and

instructing the testing circuit to interrogate the electronic circuit using a second interrogation.

41-56. -56. (canceled)