LOW-SWING CMOS INPUT CIRCUIT
First Claim
1. A CMOS input circuit comprising:
- a first power terminal (VDD, VSS);
a CMOS input stage (InvI) comprising a first switching transistor (MI, M2), the first switching transistor (M1, M2) comprising;
a first gate for receiving an input voltage (Vin),a first drain for supplying an output voltage (VoutI), anda first source, wherein a first main current path (CP) is arranged between the first source and the first; and
a leveling circuit (LC) comprising a leveling transistor (M3) having a leveling circuit main current path (MCP) and a gate electrode (GE), the leveling circuit (LC) being arranged for receiving the input voltage (Vin) and a second voltage associated with the output voltage (Vout1), the leveling circuit main current path (MCP) of the leveling transistor (M3) being electrically connected between the first main current path (CP) of the first switching transistor (MI, M2) and the first power terminal (VDD, VSS), and whereinthe first source is connected to a junction of the first main current path (CP) of the first switching transistor (MI, M2) and the leveling circuit main current path (MCP) of the leveling transistor (M3), andthe leveling circuit (LC) is constructed for arranging, under control of the second voltage, the leveling transistor (M3)(i) as a forward-biased diode-connected transistor for regulating a voltage (VI) on the first source, for reducing a gate-source voltage of the first switching transistor (MI, M2) when the input voltage (Vin) assumes a level associated with a first logical level causing the first switching transistor (MI, M2) to be switched off, and(ii) as a conductive path when the input voltage (Vin) assumes a level associated with a second logical level causing the first switching transistor (MI, M2) to be switched on.
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Accused Products
Abstract
The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according to the invention comprises a leveling circuit (LC) that is constructed for arranging, under control of a voltage associated with an output voltage of a CMOS input stage (Inv1), a leveling transistor (M3) which is located in a supply path of the CMOS input stage (Inv1), (i) as a forward-biased diode-connected transistor for regulating the voltage on a source of the CMOS input stage (Inv1) for reducing the gate-source voltage of a switching transistor (M1, M2) in the CMOS input stage (Inv1), when an input voltage of the CMOS input circuit assumes a level associated with a first logical level causing the switching transistor (M1, M2) to be switched off, and (ii) as a conductive path when the input voltage assumes a level associated with a second logical level causing the switching transistor (M1, M2) to be switched on. The invention also relates to an Input-Output circuit, an electronic circuit and a semiconductor device comprising such CMOS input circuit. The invention provides an alternative to known CMOS input circuit that make use of a diode-connected transistor that is short-circuited in case of one of the input voltage levels. An advantageous embodiment of the invention incorporates a positive feedback mechanism that makes the circuit more suitable for low supply voltages.
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Citations
16 Claims
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1. A CMOS input circuit comprising:
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a first power terminal (VDD, VSS); a CMOS input stage (InvI) comprising a first switching transistor (MI, M2), the first switching transistor (M1, M2) comprising; a first gate for receiving an input voltage (Vin), a first drain for supplying an output voltage (VoutI), and a first source, wherein a first main current path (CP) is arranged between the first source and the first; and a leveling circuit (LC) comprising a leveling transistor (M3) having a leveling circuit main current path (MCP) and a gate electrode (GE), the leveling circuit (LC) being arranged for receiving the input voltage (Vin) and a second voltage associated with the output voltage (Vout1), the leveling circuit main current path (MCP) of the leveling transistor (M3) being electrically connected between the first main current path (CP) of the first switching transistor (MI, M2) and the first power terminal (VDD, VSS), and wherein the first source is connected to a junction of the first main current path (CP) of the first switching transistor (MI, M2) and the leveling circuit main current path (MCP) of the leveling transistor (M3), and the leveling circuit (LC) is constructed for arranging, under control of the second voltage, the leveling transistor (M3) (i) as a forward-biased diode-connected transistor for regulating a voltage (VI) on the first source, for reducing a gate-source voltage of the first switching transistor (MI, M2) when the input voltage (Vin) assumes a level associated with a first logical level causing the first switching transistor (MI, M2) to be switched off, and (ii) as a conductive path when the input voltage (Vin) assumes a level associated with a second logical level causing the first switching transistor (MI, M2) to be switched on. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification