CLOCK SIGNAL DISTRIBUTING DEVICE

• US 20110006850A1
• Filed: 06/23/2010
• Published: 01/13/2011
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: SHIBASAKI, Takayuki, TAMURA, Hirotaka
• Granted Patent: US 8,258,882 B2
• Time in Patent Office: Days
• US Class Current: 331/55
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

Claims

1. A clock signal distributing device comprising:

a plurality of LC resonant oscillators, each resonating at a frequency corresponding to values of a first inductor and a first capacitor to oscillate a signal;

an injection locked LC resonant oscillator that resonates at a frequency corresponding to values of a second inductor and a second capacitor to oscillate a signal that is synchronous with an input clock signal; and

transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and of the injection locked LC resonant oscillator.

2. The clock signal distributing device according to claim 1, wherein

the first capacitors in the plurality of LC resonant oscillators and the second capacitor in the injection locked LC resonant oscillator are variable capacitors whose capacitance values are controlled with a digital signal, and

resonance frequencies of the plurality of LC resonant oscillators and of the injection locked LC resonant oscillator are determined in accordance with the values of the variable capacitors.

3. The clock signal distributing device according to claim 1, wherein

the transmission lines comprise one-dimensional wiring or two-dimensional meshed wiring.

4. The clock signal distributing device according to claim 1, wherein

the transmission lines comprise resistive elements.

5. The clock signal distributing device according to claim 1, wherein

the injection locked LC resonant oscillator oscillates the signal at a frequency obtained by dividing the frequency of the input clock signal.

6. The clock signal distributing device according to claim 1, wherein

the transmission lines connect the oscillation nodes of the plurality of LC resonant oscillators and of the injection locked LC resonant oscillator at same intervals.

7. The clock signal distributing device according to claim 1, wherein

the plurality of LC resonant oscillators and the injection locked LC resonant oscillator oscillate the signals that have the same frequency and phase.

8. The clock signal distributing device according to claim 1, further comprising:

a plurality of blocks, each block including the plurality of LC resonant oscillators, the injection locked LC resonant oscillator and the transmission lines, wherein

the same input clock signal is input into the injection locked LC resonant oscillators in the plurality of blocks.

9. The clock signal distributing device according to claim 1, wherein

the injection locked LC resonant oscillator includes:

a first p-channel field effect transistor having a gate connected to a first node, a source connected to a supply potential node and a drain connected to a second node;

a second p-channel field effect transistor having a gate connected to the second node, a source connected to the supply potential node and a drain connected to the first node;

a first n-channel field effect transistor having a gate connected to the first node and a drain connected to the second node;

a second n-channel field effect transistor having a gate connected to the second node and a drain connected to the first node;

a third n-channel field effect transistor having a gate connected to a node of the input clock signal and a drain connected to the source of the first n-channel field effect transistor;

a fourth n-channel field effect transistor having a gate connected to a node of an inverted signal of the input clock signal and a drain connected to the source of the second n-channel field effect transistor; and

a fifth n-channel field effect transistor having a source connected to a reference potential node and a drain connected to the sources of the third and fourth n-channel field effect transistors, wherein

the second inductor is connected between the first and second nodes, and

the second capacitor is connected between the first and second nodes.

10. The clock signal distributing device according to claim 1, wherein

the injection locked LC resonant oscillator includes:

a first p-channel field effect transistor having a gate connected to a first node, a source connected to a supply potential node and a drain connected to a second node;

a second p-channel field effect transistor having a gate connected to the second node, a source connected to the supply potential node and a drain connected to the first node;

a first n-channel field effect transistor having a gate connected to the first node and a drain connected to the second node;

a second n-channel field effect transistor having a gate connected to the second node and a drain connected to the first node;

a third n-channel field effect transistor having a source connected to a reference potential node and a drain connected to the sources of the first and second n-channel field effect transistors; and

a third capacitor connected between the node of the input clock signal and the gate of the third n-channel field effect transistor, wherein

the second inductor is connected between the first and second nodes, and

the second capacitor is connected between the first and second nodes.