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Clock Data Recovery Circuit Capable of Generating Clock Signal Synchronized with Data Signal

  • US 20110007855A1
  • Filed: 09/16/2010
  • Published: 01/13/2011
  • Est. Priority Date: 07/05/2005
  • Status: Active Grant
First Claim
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1. A semiconductor circuit device comprising:

  • a reception circuit receiving a reception data signal and outputting a data signal;

    a flip-flop circuit receiving the data signal from the reception circuit in synchronization with a clock signal, anda clock data recovery circuit receiving the signal from the reception circuit and outputting the clock signal to the flip-flop circuit,said clock data recovery circuit including;

    a first detection portion detecting a phase difference between said data signal and said clock signal;

    a variable delay portion varying a delay of a clock in accordance with a control code; and

    a code changing portion changing a value of said control code,said code changing portion including;

    a second detection portion detecting a value of a control code corresponding to a delay equal to one period of said clock signal,a storage portion storing the value of the control code detected by said second detection portion, andan operation portion adding or subtracting at a time the value stored in said storage portion to or from the control code when a delay amount of said variable delay portion exceeds one period of the clock in synchronizing said clock signal with said data signal while changing said control code in accordance with a detection result by said first detection portion.

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