PHASE-LOCKED LOOP CIRCUIT AND COMMUNICATION APPARATUS

• US 20110007859A1
• Filed: 05/28/2010
• Published: 01/13/2011
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Uozumi, Toshiya, Ueda, Keisuke, Endo, Ryo
• Granted Patent: US 8,331,520 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/1077 by changing characteristics of the phase or frequency detection means H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.

Claims

1. A phase-locked loop circuit comprising:

an oscillator operable to oscillate at a frequency corresponding to a phase difference signal;

a divider operable to generate a first clock obtained by dividing an output of the oscillator and a second clock higher than the first clock in frequency; and

a phase comparator,

wherein the phase comparator includes;

a first detector which receives the first clock, the second clock, and a reference clock, detects a phase difference between the first clock and the reference clock to an accuracy of a first time period given by a cycle of the second clock, and outputs the phase difference signal corresponding to the detected phase difference until the detected phase difference reaches a predetermined range; and

a second detector which receives the first clock and the reference clock, detects the phase difference between the first clock and the reference clock to an accuracy of a second time period shorter than the first time period after the phase difference detected by the first detector reaches the predetermined range, and outputs the phase difference signal corresponding to the detected phase difference.

2. The phase-locked loop circuit according to claim 1,

wherein the first detector detects the phase difference between the first clock and the reference clock by counting a clock number of the second clock, and

wherein the second detector detects the phase difference between the first clock and the reference clock, by delaying one of the first clock and the reference clock every the second time period to generate a delayed signal and by comparing the delayed signal with the other one of the first clock and the reference clock.

3. The phase-locked loop circuit according to claim 1,

wherein the phase comparator further includes

a phase determination unit operable to determine whether one of the first clock and the reference clock is leading or delayed in phase with respect to the other one of the first clock and the reference clock, and

wherein, in accordance with the determination result of the phase determination unit, the second detector outputs the phase difference signal corresponding to the phase difference between the first clock and the reference clock in the case of leading phase, and outputs the phase difference signal corresponding to zero phase difference in the case of delayed phase.

4. The phase-locked loop circuit according to claim 1,

wherein the phase comparator further includes:

a phase shifter operable to shift, by a predetermined amount, phase of either one of the first clock and the reference clock which are inputted to the first detector;

a first offset adder operable to add an offset to an output of the first detector so as to make the output of the first detector be locked at near a central value of the output range thereof; and

a second offset adder operable to add an offset to an output of the second detector so as to make the output of the second detector be locked at near a central value of the output range thereof.

5. The phase-locked loop circuit according to claim 1, further comprising:

a loop filter which limits, to a variable bandwidth, the phase difference signal outputted by the phase comparator and outputs the bandwidth-limited phase difference signal to the oscillator,

wherein the bandwidth of the loop filter after a first point of time when the phase difference detected by the first detector reaches the predetermined range is narrower than the bandwidth before the first point of time.

6. A phase-locked loop circuit having a first operation mode and a second operation mode, the phase-locked loop circuit comprising:

an oscillator operable to oscillate at a frequency corresponding to a phase difference signal;

a divider operable to generate a first clock obtained by dividing an output of the oscillator and a second clock higher than the first clock in frequency; and

a phase comparator,

wherein the phase comparator includes;

a first detector which receives the first clock, the second clock, and a reference clock and detects a phase difference between the first clock and the reference clock to an accuracy of a first time period given by a cycle of the second clock;

a switching unit which receives the first clock and the second clock and outputs the first clock in the second operation mode and the second clock in the first operation mode;

a second detector which receives an output of the switching unit and the reference clock and detects the phase difference between the output of the switching unit and the reference clock to an accuracy of a second time period shorter than the first time period; and

a phase difference signal generating unit which generates the phase difference signal,

wherein, in the first operation mode, the second detector detects the phase difference in parallel with the first detector, and the phase difference signal generating unit generates the phase difference signal by composing the phase differences detected by the first detector and the second detector, and

wherein, in the second operation mode, the second detector starts to detect the phase difference from a first point of time when the phase difference detected by the first detector reaches a predetermined range, and the phase difference signal generating unit outputs the phase difference signal corresponding to the phase difference detected by the first detector until the first point of time, and outputs the phase difference signal corresponding to the phase difference detected by the second detector after the first point of time.

7. The phase-locked loop circuit according to claim 6,

wherein the first detector detects the phase difference between the first clock and the reference clock by counting a clock number of the second clock, and

wherein the second detector detects the phase difference between the output of the switching unit and the reference clock, by delaying one of the output of the switching unit and the reference clock every the second time period to generate a delayed signal and by comparing the delayed signal with the other one of the output of the switching unit and the reference clock.

8. A communication apparatus having a first operation mode and a second operation mode and sending transmitting data, the communication apparatus comprising:

an oscillator operable to oscillate at a frequency corresponding to a phase difference signal;

a modulator which receives an output of the oscillator and, in the second operation mode, modulates the output of the oscillator by the transmitting data after the oscillating frequency of the oscillator stabilizes;

a divider which generates a first clock obtained by dividing the output of the oscillator and a second clock higher than the first clock in frequency;

a dividing ratio controller which changes a dividing ratio of the divider in the first operation mode, according to the transmitting data after the oscillating frequency of the oscillator stabilizes; and

a phase comparator,

wherein the phase comparator includes;

a first detector which receives the first clock, the second clock, and a reference clock, and detects a phase difference between the first clock and the reference clock to an accuracy of a first time period given by a cycle of the second clock;

a switching unit which receives the first clock and the second clock and outputs the first clock in the second operation mode and the second clock in the first operation mode;

a second detector which receives an output of the switching unit and the reference clock and detects a phase difference between the output of the switching unit and the reference clock to an accuracy of a second time period shorter than the first time period; and

a phase difference signal generating unit which generates the phase difference signal,

wherein, in the first operation mode, the second detector detects the phase difference in parallel with the first detector, and the phase difference signal generating unit generates the phase difference signal by composing the phase differences detected by the first detector and the second detector, and

wherein, in the second operation mode, the second detector starts to detect the phase difference from a first point of time when the phase difference detected by the first detector reaches a predetermined range, and the phase difference signal generating unit outputs the phase difference signal corresponding to the phase difference detected by the first detector until the first point of time and outputs the phase difference signal corresponding to the phase difference detected by the second detector after the first point of time.

9. A communication apparatus having a first operation mode for sending transmitting data and a second operation mode for receiving a reception signal, the communication apparatus comprising:

an oscillator operable to oscillate at a frequency corresponding to a phase difference signal;

a mixer operable to mix an output of the oscillator and the reception signal in the second operation mode, after the oscillating frequency of the oscillator stabilizes;

a divider operable to generate a first clock obtained by dividing the output of the oscillator and a second clock higher than the first clock in frequency;

a dividing ratio controller operable to change a dividing ratio of the divider in the first operation mode, according to the transmitting data; and

a phase comparator,

wherein the phase comparator includes;

a first detector which receives the first clock, the second clock, and a reference clock, and detects a phase difference between the first clock and the reference clock to an accuracy of a first time period given by a cycle of the second clock;

a switching unit which receives the first clock and the second clock and outputs the first clock in the second operation mode and the second clock in the first operation mode;

a second detector which receives an output of the switching unit and the reference clock and detects a phase difference between the output of the switching unit and the reference clock to an accuracy of a second time period shorter than the first time period; and

a phase difference signal generating unit operable to generate the phase difference signal,

wherein, in the first operation mode, the second detector detects the phase difference in parallel with the first detector, and the phase difference signal generating unit generates the phase difference signal by composing the phase differences detected by the first detector and the second detector, and

wherein, in the second operation mode, the second detector starts to detect the phase difference from a first point of time when the phase difference detected by the first detector reaches a predetermined range, and the phase difference signal generating unit outputs the phase difference signal corresponding to the phase difference detected by the first detector until the first point of time, and outputs the phase difference signal corresponding to the phase difference detected by the second detector after the first point of time.