SYSTEM FOR CONVERGENCE EVALUATION FOR STATIONARY METHOD ITERATIVE LINEAR SOLVERS
First Claim
1. A system for evaluating the convergence to a solution for a matrix equation, the system comprising:
- at least one field programmable gate array (FPGA), including a plurality of configurable logic elements and a plurality of configurable storage elements;
a conversion element formed from the configurable logic elements and configured to determine the absolute value of each of a plurality of updates;
a summation unit formed from the configurable logic elements and configured to accumulate the absolute value of the plurality of updates to form a total sum; and
a comparator formed from the configurable logic elements and configured to compare the total sum to a convergence factor.
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Accused Products
Abstract
A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.
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Citations
16 Claims
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1. A system for evaluating the convergence to a solution for a matrix equation, the system comprising:
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at least one field programmable gate array (FPGA), including a plurality of configurable logic elements and a plurality of configurable storage elements; a conversion element formed from the configurable logic elements and configured to determine the absolute value of each of a plurality of updates; a summation unit formed from the configurable logic elements and configured to accumulate the absolute value of the plurality of updates to form a total sum; and a comparator formed from the configurable logic elements and configured to compare the total sum to a convergence factor. - View Dependent Claims (2, 3, 4, 5)
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6. A system for evaluating the convergence to a solution for a matrix equation, the system comprising:
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a plurality of field programmable gate arrays (FPGAs), each including a plurality of configurable logic elements and a plurality of configurable storage elements; a plurality of update summation units each including— a storage element formed from the configurable storage elements and configured to store a portion of a plurality of updates, a conversion element formed from the configurable logic elements and configured to determine the absolute value of each of the portion of the plurality of updates, and a first summation unit formed from the configurable logic elements and configured to accumulate the absolute value of the portion of the plurality of updates to form a partial sum; and a global convergence unit including— a second summation unit formed from the configurable logic elements and configured to accumulate the partial sums from each update summation unit to form a total sum, and a comparator formed from the configurable logic elements and configured to generate a signal if the total sum is less than a convergence factor. - View Dependent Claims (7, 8, 9, 10)
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11. A method of evaluating the convergence to a solution for a matrix equation, the method comprising the steps of:
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a) receiving in a field programmable gate array (FPGA) a plurality of updates from an external iterative linear solver; b) determining the absolute value of each of the plurality of updates utilizing a conversion element in the FPGA; c) accumulating the absolute value of the plurality of updates utilizing a summation unit in the FPGA; d) comparing the accumulated value to a convergence factor utilizing a comparator in the FPGA; and e) generating a signal if the accumulated value is less than the convergence factor. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification