MASSIVE MULTI-CORE PROCESSOR BUILT WITH SERIAL SWITCHING

• US 20110010481A1
• Filed: 07/10/2009
• Published: 01/13/2011
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Hamadani, Mehrdad, Kancherla, Mani, Cheung, David, Bansal, Deepak, Malli, Sreenivasulu, Moy, Sam Htin, Devarapalli, Sridhar
• Granted Patent: US 8,335,884 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.

Claims

1. A multi-processor architecture comprising:

a first plurality of processors that control the routing of packets;

a first PCI-Express (PCIe) switch, wherein each of the first plurality of processors is coupled to the first PCIe switch by a point-to-point serial link;

first packet processing logic coupled to the first PCIe switch by a point-to-point serial link, wherein data packets are transferred between the first packet processing logic and the first plurality of processors through the first PCIe switch.

2. The multi-processor architecture of claim 1, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first barrel card.

3. The multi-processor architecture of claim 1, wherein the first packet processing logic implements posted write direct memory access (DMA) operations to the first plurality of processors.

4. The multi-processor architecture of claim 1, further comprising:

a second plurality of processors;

a second PCIe switch, wherein each of the second plurality of processors is coupled to the second PCIe switch by a point-to-point serial link;

second packet processing logic coupled to the second PCIe switch by a point-to-point serial link, wherein packets are transferred between the second packet processing logic and the second plurality of processors through the second PCIe switch.

5. The multi-processor architecture of claim 4, further comprising a third PCIe switch coupling the first and second PCIe switches.

6. The multi-processor architecture of claim 5, further comprising a first management processor coupled to the third PCIe switch.

7. The multi-processor architecture of claim 6, further comprising a first processor accelerator coupled to the third PCIe switch.

8. The multi-processor architecture of claim 7, further comprising:

a second management processor coupled to the third PCIe switch; and

a second processor accelerator coupled to the third PCIe switch.

9. The multi-processor architecture of claim 5, further comprising a fourth PCIe switch coupled to the third PCIe switch.

10. The multi-processor architecture of claim 9, further comprising:

one or more line cards that transmit and receive packets; and

a switch fabric that couples each of the one or more line cards to the first packet processing logic and the second packet processing logic, wherein the fourth PCIe switch is coupled to each of the one or more line cards and the switch fabric.

11. The multi-processor architecture of claim 4, wherein the first plurality of processors, the first PCIe switch and the first packet processing logic are located on a first barrel card, and the second plurality of processors, the second PCIe switch and the second packet processing logic are located on a second barrel card.

12. A multi-processor architecture comprising:

a plurality of barrel cards, each including;

a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch; and

a first external PCIe switch coupled to each PCIe switch of the plurality of barrel cards.

13. The multi-processor architecture of claim 12, further comprising a management processor coupled to the first external PCIe switch.

14. The multi-processor architecture of claim 13, further comprising a processor accelerator coupled to the first external PCIe switch.

15. The multi-processor architecture of claim 12, further comprising:

one or more line cards that receive and transmit data packets; and

a switch fabric coupling each of the one or more line cards to the packet processing logic of each of the plurality of barrel cards.

16. The multi-processor architecture of claim 15, further comprising a second external PCIe switch coupled to the first external PCIe switch, the one or more line cards and the switch fabric.

17. A method of implementing a multi-processor architecture comprising:

receiving a first packet with a first barrel card that includes a first plurality of multi-core processors;

routing the first packet to one of the first plurality of multi-core processors through a first PCI-Express (PCIe) switch on the first barrel card.

18. The method of claim 17, further comprising routing the first packet through the first PCIe switch on a plurality of point-to-point serial links.

19. The method of claim 17, further comprising implementing a posted write direct memory access (DMA) process when routing the first packet to one of the first plurality of multi core processors.

20. The method of claim 17, further comprising:

receiving a second packet with a second barrel card that includes a second plurality of multi-core processors;

routing the second packet to one of the second plurality of multi-core processors through a second PCIe switch on the second barrel card.

21. The method of claim 20, further comprising routing the first packet through a switch fabric to the first barrel card;

and

routing the second packet through the switch fabric to the second barrel card.