LOGICAL BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND CONTROL CIRCUIT STORAGE SYSTEM USING THE SAME

• US 20110010489A1
• Filed: 09/02/2009
• Published: 01/13/2011
• Est. Priority Date: 07/09/2009
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: YEH, CHIH-KANG
• Granted Patent: US 9,098,395 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A logical block management method for managing a plurality of logical blocks of a flash memory device is provided. The logical block management method includes providing a flash memory controller, grouping the logical blocks into a plurality of logical zones, wherein each logical block maps to one of the logical zones. The logical block management method also includes counting a use count value for each logical block, and dynamically adjusting mapping relations between the logical blocks and the logical zones according to the use count values. Accordingly, the logical block management method can effectively utilizing the logical zones to determine usage patterns of the logical blocks and use different mechanisms to write data, so as to increase the performance of the flash memory storage device.

Claims

1. A logical block management method, for managing a plurality of logical blocks of a flash memory storage device, the logical block management method comprising:

providing a flash memory controller;

grouping the logical blocks into a plurality of logical zones;

recording mapping relations between the logical blocks and the logical zones, wherein each of the logical blocks maps to one of the logical zones;

counting a use count value for each of the logical blocks; and

adjusting the mapping relations between the logical blocks and the logical zones by using the flash memory controller according to the use count values.

2. The logical block management method as claimed in claim 1, the step of recording the mapping relations between the logical blocks and the logical zones comprises:

establishing a logical block-logical zone mapping table to record the mapping relations between the logical blocks and the logical zones.

3. The logical block management method as claimed in claim 1, wherein the logical zones at least comprise a hot logical zone and a cold logical zone.

4. The logical block management method as claimed in claim 3, wherein the step of adjusting the mapping relations between the logical blocks and the logical zones by the flash memory controller according to the use count values comprises:

determining whether the use count values of the logical blocks in the cold logical zone is greater than a use count threshold value; and

when the use count value of one of the logical blocks in the cold logical zone is greater than the use count threshold value, grouping the one of the logical block into the hot logical zone, selecting one of the logical blocks from the hot logical zone, and grouping the selected logical block into the cold logical zone.

5. The logical block management method as claimed in claim 4, wherein the use count value of the selected logical block is not greater than the use count values of the other logical blocks in hot the logical zone.

6. The logical block management method as claimed in claim 1, wherein the use count values comprise times for a host system sending write commands to the logical blocks or the number of sectors of data written into the logical blocks.

7. The logical block management method as claimed in claim 1, further comprising adjusting the use count values by using the flash memory controller, wherein the use count values are set to zero or recalculated according to an algorithm.

8. A flash memory control circuit, for managing a plurality of logical blocks of a flash memory storage device, the flash memory control circuit comprises:

a microprocessor unit;

a flash memory interface unit, coupled to the microprocessor unit;

a host interface unit, coupled to the microprocessor unit; and

a block management unit, coupled to the microprocessor unit and used to group the logical blocks into a plurality of logical zones, and count a use count value for each of the logical blocks,

wherein the block management unit adjusts mapping relations between the logical blocks and the logical zones according to the use count values.

9. The flash memory control circuit as claimed in claim 8, wherein the block management unit comprises:

a memory management unit, used to record the mapping relations between the logical blocks and the logical zones, wherein each of the logical blocks maps to one of the logical zones; and

a use count unit, used to count the use count value for each of the logical blocks.

10. The flash memory control circuit as claimed in claim 9, wherein the memory management unit records the mapping relations between the logical blocks and the logical zones in a logical block-logical zone mapping table.

11. The flash memory control circuit as claimed in claim 9, wherein the logical zones at least comprise a hot logical zone and a cold logical zone.

12. The flash memory control circuit as claimed in claim 11, wherein the memory management unit determines whether the use count values of the logical blocks in the cold logical zone is greater than a use count threshold value,

wherein when the use count value of one of the logical blocks is greater than the use count threshold value, the memory management unit groups the one of the logical block into the hot logical zone, selects one of the logical blocks from the hot logical zone, and groups the selected logical block into the cold logical zone.

13. The flash memory control circuit as claimed in claim 12, wherein the use count value of the selected logical block is not greater than the use count values of the other logical blocks in the hot logical zone.

14. The flash memory control circuit as claimed in claim 8, wherein the use count values comprise times for a host system sending write commands to the logical blocks or the number of sectors of data written into the logical blocks.

15. A flash memory storage system, comprising:

a connector;

a flash memory chip; and

a flash memory controller, coupled to the connector and the flash memory chip and used to configure a plurality of logical blocks, group the logical blocks into a plurality of logical zones, and record mapping relations between the logical blocks and the logical zones, wherein each of the logical blocks maps to one of the logical zones,

wherein the flash memory controller is further used to count a use count value for each of the logical blocks, and adjusting the mapping relations between the logical blocks and the logical zones according to the use count values.

16. The flash memory storage system as claimed in claim 15, wherein the flash memory controller records the mapping relations between the logical blocks and the logical zones in a logical block-logical zone mapping table.

17. The flash memory storage system as claimed in claim 15, wherein the logical zones at least comprise a hot logical zone and a cold logical zone.

18. The flash memory storage system as claimed in claim 17, wherein the flash memory controller determines whether the use count values of the logical blocks in the cold logical zone is greater than a use count threshold value,

wherein when the use count value of one of the logical blocks is greater than the use count threshold value, the flash memory controller groups the one of the logical block into the hot logical zone, selects one of the logical blocks from the hot logical zone, and groups the selected logical block into the cold logical zone.

19. The flash memory storage system as claimed in claim 18, wherein the use count value of the selected logical block is not greater than the use count values of the other logical blocks in the hot logical zone.

20. The flash memory storage system as claimed in claim 15, wherein the use count values comprise times for a host system sending write commands to the logical blocks or the number of sectors of data written into the logical blocks.

21. A flash memory storage system, comprising:

a connector;

a flash memory chip, comprising a plurality of physical blocks; and

a flash memory controller, coupled to the connector and the flash memory chip and used to configure a plurality of logical blocks and at least group the physical blocks into a data area and a spare area, wherein each of the logical blocks maps to at least one physical block,

wherein the flash memory controller counts a use count value for each of the logical blocks, and groups at least one logical block of the logical blocks into a hot logical zone according to the use count value.

22. The flash memory storage system as claimed in claim 21, wherein the use count values comprise times for a host system sending write commands to the logical blocks or the number of sectors of data written into the logical blocks.

23. The flash memory storage system as claimed in claim 22, further comprising a temporary storage area,

wherein when written data from the host system belongs to one of the logical blocks in the hot logical zone, the flash memory controller stores the written data in the temporary storage area.

24. The flash memory storage system as claimed in claim 23, wherein the temporary storage area is a dynamic random access memory (DRAM) or a single level cell (SLC) NAND flash memory.