MULTIPROCESSOR COMMUNICATION PROTOCOL BRIDGE BETWEEN SCALAR AND VECTOR COMPUTE NODES

• US 20110010522A1
• Filed: 06/11/2010
• Published: 01/13/2011
• Est. Priority Date: 06/12/2009
• Status: Abandoned Application

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Klausler, Peter M., Abts, Dennis C., Nowicki, James
• Application Number:
  US12/814,118
• Publication Number:
  US 20110010522A1
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor interconnect network and the indirect processor interconnect network.

Claims

1. A multiprocessor computer system, comprising:

a plurality of processor nodes coupled by a direct processor interconnect network;

a plurality of processor nodes coupled by an indirect processor interconnect network; and

a bridge directly coupling the direct processor interconnect network and the indirect processor interconnect network.

2. The multiprocessor computer system of claim 1, wherein the bridge is further operable to convert between direct flow control units (flits) of the direct processor interconnect network and physical units (phits) of the indirect processor interconnect network.

3. The multiprocessor computer system of claim 1, wherein the direct processor interconnect network comprises a three-dimensional torus network, and the indirect processor interconnect network comprises a Clos network.

4. The multiprocessor computer system of claim 1, wherein a first of the indirect and direct processor interconnect networks comprises vector processors and the other of the direct and indirect processor interconnect networks comprises scalar processors.

5. The multiprocessor computer system of claim 4, wherein the system is further operable to buffer and reorder packets sent from a vector processor node to a scalar processor node such that the packets appear to arrive at the scalar processor node in order.

6. The multiprocessor computer system of claim 1, the bridge further operable to convert between different cache line sizes between the direct and indirect processor interconnect networks.

7. The multiprocessor computer system of claim 1, the bridge further operable to manage a ring buffer in an indirect network node receiving a message from a direct network node.

8. The multiprocessor computer system of claim 1, the bridge further operable to provide a flow control mechanism using result-returning atomic memory operations (AMOs) to act upon a block transfer engine (BTE), where the AMO reply indicates success or failure of the BTE work request.

9. A method of operating a multiprocessor computer system, comprising:

operating a plurality of processor nodes coupled by a direct processor interconnect network;

operating a plurality of processor nodes coupled by an indirect processor interconnect network; and

coupling the direct processor interconnect network and the indirect processor interconnect network via a bridge.

10. The method of operating a multiprocessor computer system of claim 9, further comprising converting between direct flow control units (flits) of the direct processor interconnect network and physical units (phits) of the indirect processor interconnect network.

11. The method of operating a multiprocessor computer system of claim 9, wherein the direct processor interconnect network comprises a three-dimensional torus network, and the indirect processor interconnect network comprises a Clos network.

12. The method of operating a multiprocessor computer system of claim 9, wherein a first of the indirect and direct processor interconnect networks comprises vector processors and the other of the direct and indirect processor interconnect networks comprises scalar processors.

13. The method of operating a multiprocessor computer system of claim 12, further comprising buffering and reordering packets sent from a vector processor node to a scalar processor node such that the packets appear to arrive at the scalar processor node in order.

14. The method of operating a multiprocessor computer system of claim 9, further comprising converting between different cache line sizes between the direct and indirect processor interconnect networks.

15. The method of operating a multiprocessor computer system of claim 9, further comprising managing a ring buffer in an indirect network node receiving a message from a direct network node.

16. The method of operating a multiprocessor computer system of claim 9, further comprising providing a flow control mechanism using result-returning atomic memory operations (AMOs) to act upon a block transfer engine (BTE), where the AMO reply indicates success or failure of the BTE work request.