METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES

• US 20110012085A1
• Filed: 09/24/2007
• Published: 01/20/2011
• Est. Priority Date: 09/24/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Romankiw, Lubomyr T., Huang, Qiang, Deligianni, Hariklia
• Granted Patent: US 7,892,956 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02628 using solutions
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.

Claims

1. A method of forming a vertical Field Effect Transistor (FET) comprising:

forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region by the following steps;

forming a bottom source/drain electrode on a substrate;

forming a bottom spacer layer composed of a dielectric or insulating material on said bottom source/drain electrode;

forming a gate electrode layer or layers over said bottom spacer layer;

forming an upper spacer layer composed of a dielectric or insulating material over said gate electrode layer or layers with said upper spacer layer having a top surface;

creating a columnar pore extending down from said top surface through said upper spacer layer, said gate electrode layer or layers, and said bottom spacer layer to said bottom source/drain electrode;

then etching through said columnar pore to form a recessed notch or pocket in said gate electrode layer or layers;

then forming a conformal gate dielectric layer on surfaces of said columnar pore including said recessed pocket;

then etching back said conformal gate dielectric layer from said surfaces of said columnar pore, leaving said gate dielectric layer in said recessed notch or pocket in said gate electrode layer;

then filling said columnar pore with a semiconductor material by plating to form said vertical semiconductor nanowire therein having a bottom end formed on said bottom source/drain electrode; and

then forming a top source/drain electrode in contact with a top end of said vertical semiconductor nanowire.

2. The method of claim 1 wherein said plating of said semiconductor nanowires in said columnar pore is performed by electroless deposition or electroplating by applying an electroplating potential across said bottom electrode and a conductive anode in an electrolyte with said semiconductor material selected from the group consisting of Ge, InSb, InAs, GaAs, GaSb, CdS, CdSe, CdTe, and other II-VI and III-IV compounds, whereby said semiconductor material is formed in said columnar pores thereby forming a wire-shape structure.

4. The method of claim 1 including the step of forming a capping layer over said gate electrode layer or layers comprising a dielectric material.

10. The method of claim 1 wherein the process further includes forming contacts to said bottom source/drain electrodes and to said gate electrodes.

11. The method of claim 10 wherein said contacts to said bottom source/drain electrodes are formed by the following steps:

creating recessed regions on sidewalls inside said columnar pore wherein said gate electrode layer is exposed;

forming a dielectric layer selectively on said gate electrode layer in said recessed regions; and

filling said columnar pore with conductive material.

12. The method of claim 11 including:

forming said dielectric layer in said recessed regions in said columnar pore by conformally depositing a gate dielectric material in said columnar pore; and

then removing said dielectric material from said columnar pore except for said recessed pocket on said sidewalls of said pore using directional etching of said gate dielectric layer in the vertical direction.

13. The method of claim 11 wherein said dielectric layer in said recessed pocket and in said columnar pore is formed by selectively growing dielectric material exposed in said recessed region using a selective growth method.

14. The method of claim 1 including:

forming an array of said vertical semiconductor FET devices with each having a contact to a said gate electrode, a said bottom source/drain electrode and a said top source/drain electrode;

stacking arrays of FET devices on top of each other by repeating steps to form another level of said vertical semiconductor FET devices having electroplated vertical semiconductor nanowires on top of a previous level of transistors.

15. The method of claim 1 including:

making contacts to the gate electrode, source/drain electrodes by forming columnar pores across the stack of layers on the electrode to be connected and forming interconnect via structures by filling said columnar pores with conductive layers; and

forming isolating structures to separate the transistors by patterning on top of the top source/drain electrode, by etching through the stacks of materials, and then by filling dielectric material into the etched structures.

3. (canceled)

5. (canceled)

6. A method of forming a vertical Field Effect Transistor (FET) comprising:

forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region including the steps follows;

depositing on an insulating substrate a stack of layers including a bottom source/drain electrode comprising a conductive layer, a bottom spacer layer composed of a dielectric or insulating material on said bottom source/drain electrode and a sacrificial dielectric material on said bottom spacer layer;

then creating a columnar pore in said material stack connecting to said bottom source/drain electrode by dry etching through said sacrificial dielectric material and said bottom spacer layer using a patterned mask;

then plating a semiconductor nanowire into said columnar pore to form said vertical semiconductor nanowire having a bottom end formed on said bottom source/drain electrode;

then removing said sacrificial dielectric material thereby exposing sidewalls of an upper portion of said vertical semiconductor nanowire with said bottom spacer layer remaining along remaining portions of said sidewalls of said semiconductor nanowire below said sacrificial dielectric material;

then depositing a gate dielectric layer on said sidewalls of said upper portion of said vertical semiconductor nanowire and on top of said bottom spacer layer;

then depositing a gate electrode layer or layers on top of said gate dielectric layer;

then forming a an upper spacer layer on top of said gate electrode layer or layers;

then planarizing said vertical semiconductor nanowire and said upper spacer layer; and

then depositing a top source/drain electrode layer in contact with said vertical semiconductor nanowire.

7. The method of claim 6 wherein said plating of said semiconductor nanowires in said columnar pore is performed by applying an electroplating potential across said bottom electrode and a conductive anode in an electrolyte with a semiconductor material selected from the group consisting of Ge, InSb, InAs, GaAs, GaSb, CdS, CdSe, CdTe, and other II-VI and III-IV compounds, whereby the semiconductor materials is formed in the columnar pores thereby forming a wire-shaped structure.

8. A method of forming a vertical Field Effect Transistor (FET) comprising:

forming an FET device comprising an FET channel region located between a doped source region and a doped drain region in a vertical semiconductor nanowire with said doped source region and said doped drain region formed in distal ends of said vertical semiconductor nanowire aside from said channel region by the following steps;

depositing a stack of layers on an insulating substrate, said stack of layers including a bottom source/drain electrode composed of conductive material, a bottom spacer layer, and a gate electrode layer or layers;

then creating a via structure in said gate electrode layer by etching said gate electrode layer or layers using an etching mask;

then depositing a gate dielectric material to fill said via structure in said gate electrode layer and polishing said gate dielectric material;

then depositing a second dielectric spacer layer;

then forming an etching mask on top of the second spacer layer having a mask via aligned with a gate electrode via in said gate electrode layer, wherein said mask via in said etching mask is slightly smaller than said gate electrode via in said gate electrode layer or layers;

then creating a columnar pore having a top and a bottom extending through said stack of layers using a directional dry etching process with said etching mask, wherein said columnar pore connects to said bottom source/drain electrode below said stack of layers extending through said top spacer layer, said gate dielectric layer or layers and said bottom spacer layer without touching said gate electrode layer, wherein said gate dielectric material remaining in said gate electrode vias of said gate electrode layer is continuous;

then electroplating said vertical semiconductor nanowire into said columnar pore by applying a plating current or potential across said bottom source/drain electrode and a conductive anode in an electrolyte, where a semiconductor material is formed in said columnar pores thereby forming a wire-shaped structure;

then polishing and planarizing the top surface of said vertical semiconductor nanowire and said upper spacer layer; and

then depositing a top conductive layer as a second source or drain electrode layer.

9. The method of claim 8 including the step of depositing a capping material on top of said gate electrode layer.

16. A vertical Field Effect Transistor (FET) comprising:

a substrate composed of a material selected from the group consisting of nonconductive and highly resistive semiconductor materials;

a bottom electrode comprising a conductive layer formed on top of said substrate;

a bottom spacer layer formed on a top surface of said bottom electrode with a columnar pore extending therethrough down to said top surface of said bottom electrode;

a vertical semiconductor nanowire having a bottom end and a top end with said semiconductor nanowire filling said pore and said bottom end being in contact with said top surface of said bottom electrode;

said vertical semiconductor nanowire comprising an FET channel in a central region thereof between with doped source and drain regions at opposite ends of said nanowire;

a gate dielectric structure formed on an exterior surface of said vertical semiconductor nanowire above said bottom spacer layer;

a gate electrode formed on an exterior surface of said gate dielectric structure;

an upper spacer layer surrounding said vertical semiconductor nanowire formed above said gate electrode; and

a top electrode formed above said upper spacer layer; and

said gate electrode being separated from said bottom electrode by said bottom spacer layer and being separated from said top electrode by said upper spacer layer.

17. The vertical FET of claim 16 wherein said gate electrode is located in a middle portion of said nanowire between said bottom end and said top end.

18. The vertical FET of claim 16 wherein said semiconductor nanowire comprises germanium (Ge) nanowire.

19. The vertical FET of claim 16 wherein:

said columnar pore extends through both said upper spacer layer and said bottom spacer layer to said bottom electrode; and

said vertical semiconductor nanowire is contained within said columnar pore.

20. The vertical FET of claim 19 including:

an array of FET devices with each having a contact to a said gate electrode, a said bottom electrode and a said top electrode; and

stacked arrays of FET devices on top of each other by repeating steps to form another level of vertical FETs having electroplated vertical semiconductor nanowires on top of the previous level of transistors.